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Old 09-12-2007, 09:58 AM
lexluthor
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Default [Nios II] How fast the cpu in Nios II can reach in the Cycone ?



Can it reach 100 DMIPS £¿

I give the cpu 100MHz clk, and use the Fast Core.

There is a program:

void main()
{
while(1)
{
IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, data++);
}
}

The frequence of change of the outputs can reach 100 MHz?

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Old 09-12-2007, 02:05 PM
G¨®rski Adam
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Default Re: [Nios II] How fast the cpu in Nios II can reach in the Cycone?

lexluthor pisze:
>
> Can it reach 100 DMIPS £¿
>
> I give the cpu 100MHz clk, and use the Fast Core.
>
> There is a program:
>
> void main()
> {
> while(1)
> {
> IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, data++);
> }
> }
>
> The frequence of change of the outputs can reach 100 MHz?
>


No. Take a look over assembler file. It's not a single instruction.
Additionaly NIOS need more than one clk cycle for instruction execution
( or maybe not)
But anyway you can add hardware extension for special request (like
parallel to serial hardware conversion)

Adam
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  #3 (permalink)  
Old 09-12-2007, 04:36 PM
Iwo Mergler
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Default Re: [Nios II] How fast the cpu in Nios II can reach in the Cycone ?

lexluthor wrote:

>
>
> Can it reach 100 DMIPS ?
>
> I give the cpu 100MHz clk, and use the Fast Core.
>
> There is a program:
>
> void main()
> {
> while(1)
> {
> IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, data++);
> }
> }
>
> The frequence of change of the outputs can reach 100 MHz?


Short answer: no.

Medium answer:

Your code will look roughly like this in pseudo-assembler:

load R1,PIO_0_BASE # target address
load R2,0 # data initialization
loop:
store R2,[R1]
incr R2
jump loop

The fast version of NIOS II takes roughly two clock
cycles per instruction - a 100MHz clock should give
you around 50MIPS best case.

In your loop you will need three instructions per iteration.
The code will fit into the single-cycle cache, freeing
up the bus.

The PIO implementation uses a single cycle write, so assuming
you placed it on the same bus as the processor, this won't
be a bottleneck.

So your best-case rate of change on the PIO port
is a little under 17MHz.

Kind regards,

Iwo

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  #4 (permalink)  
Old 09-13-2007, 03:00 AM
Ben Jackson
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Default Re: [Nios II] How fast the cpu in Nios II can reach in the Cycone ?

On 2007-09-12, lexluthor <[email protected]> wrote:
>
>
> while(1)
> {
> IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, data++);
> }
>
> The frequence of change of the outputs can reach 100 MHz?


I've not used it, but I think Altera's C2H can take code similar to
that and wrap a custom DMA engine around it automagically. Or so
the FAE said!

--
Ben Jackson AD7GD
<[email protected]>
http://www.ben.com/
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