Re: [Nios II] How fast the cpu in Nios II can reach in the Cycone ?
lexluthor wrote:
>
>
> Can it reach 100 DMIPS ?
>
> I give the cpu 100MHz clk, and use the Fast Core.
>
> There is a program:
>
> void main()
> {
> while(1)
> {
> IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, data++);
> }
> }
>
> The frequence of change of the outputs can reach 100 MHz?
Short answer: no.
Medium answer:
Your code will look roughly like this in pseudo-assembler:
load R1,PIO_0_BASE # target address
load R2,0 # data initialization
loop:
store R2,[R1]
incr R2
jump loop
The fast version of NIOS II takes roughly two clock
cycles per instruction - a 100MHz clock should give
you around 50MIPS best case.
In your loop you will need three instructions per iteration.
The code will fit into the single-cycle cache, freeing
up the bus.
The PIO implementation uses a single cycle write, so assuming
you placed it on the same bus as the processor, this won't
be a bottleneck.
So your best-case rate of change on the PIO port
is a little under 17MHz.
Kind regards,
Iwo
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