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  #1 (permalink)  
Old 05-21-2009, 04:26 PM
jacko
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Default Nibz VHDL Processor (Version G-spot)

Hi

72MHz it's hot! But cool. Lower un-necessary D_O pin state transitions
etc. Estimated 17 MIPS on 8 bit bus.

http://nibz.goglecode.com for download. Any improvements for speed or
power efficiency while keeping low area welcome.

BSD license, or 1 core (instruction stream) per chip (packaged
semiconductor or logic substrate) license.

44% of MAX II 1270 C5 (527 LEs in speed technology)

8 Bit data bus, and ALU now 8 bit pipelined, as 16 bit is same space
with no pipeline. ALU completion in following instruction fetch. 16
bit ISA. Stack style of programming.

Clock possibly higher as critical path driven from latched value
register.

Interleave RW for full cycle RW_O = '0' on both hi and low byte (quite
a large part of the design).

A full Moore machine, all outputs driven by registers. In full custom
this allows the large IO pad drivers to provide the feedback. Much of
the instruction decode is pipelined due to most significant decoded
bits are in the low byte.

Should be suitable for interfacing to BRAM (with common address on
read and write) or external SRAM.

cheers jacko

p.s. much of the pipelining is only possible with a low logic area
because of the half width data bus dual fetching of data. Even though
the design is big endian, the fetches and stores are done little
endian for the usual carry propergation reasons, and for instruction
decode efficiency.
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  #2 (permalink)  
Old 05-21-2009, 05:45 PM
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Default Re: Nibz VHDL Processor (Version G-spot)

On May 21, 5:26*pm, jacko <[email protected]> wrote:
> Hi
>
> 72MHz it's hot! But cool. Lower un-necessary D_O pin state transitions
> etc. Estimated 17 MIPS on 8 bit bus.
>
> http://nibz.goglecode.comfor download. Any improvements for speed or
> power efficiency while keeping low area welcome.
>
> BSD license, or 1 core (instruction stream) per chip (packaged
> semiconductor or logic substrate) license.
>
> 44% of MAX II 1270 C5 (527 LEs in speed technology)
>
> 8 Bit data bus, and ALU now 8 bit pipelined, as 16 bit is same space
> with no pipeline. ALU completion in following instruction fetch. 16
> bit ISA. Stack style of programming.
>
> Clock possibly higher as critical path driven from latched value
> register.
>
> Interleave RW for full cycle RW_O = '0' on both hi and low byte (quite
> a large part of the design).
>
> A full Moore machine, all outputs driven by registers. In full custom
> this allows the large IO pad drivers to provide the feedback. Much of
> the instruction decode is pipelined due to most significant decoded
> bits are in the low byte.
>
> Should be suitable for interfacing to BRAM (with common address on
> read and write) or external SRAM.
>
> cheers jacko
>
> p.s. much of the pipelining is only possible with a low logic area
> because of the half width data bus dual fetching of data. Even though
> the design is big endian, the fetches and stores are done little
> endian for the usual carry propergation reasons, and for instruction
> decode efficiency.


goglecode?

G-spot?
have you ever found it?

Antti
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  #3 (permalink)  
Old 05-21-2009, 07:43 PM
Jacko
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Posts: n/a
Default Re: Nibz VHDL Processor (Version G-spot)

On May 21, 4:45*pm, "[email protected]"
<[email protected]> wrote:
> On May 21, 5:26*pm, jacko <[email protected]> wrote:
>
>
>
> > Hi

>
> > 72MHz it's hot! But cool. Lower un-necessary D_O pin state transitions
> > etc. Estimated 17 MIPS on 8 bit bus.

>
> >http://nibz.goglecode.comfordownload. Any improvements for speed or
> > power efficiency while keeping low area welcome.

>
> > BSD license, or 1 core (instruction stream) per chip (packaged
> > semiconductor or logic substrate) license.

>
> > 44% of MAX II 1270 C5 (527 LEs in speed technology)

>
> > 8 Bit data bus, and ALU now 8 bit pipelined, as 16 bit is same space
> > with no pipeline. ALU completion in following instruction fetch. 16
> > bit ISA. Stack style of programming.

>
> > Clock possibly higher as critical path driven from latched value
> > register.

>
> > Interleave RW for full cycle RW_O = '0' on both hi and low byte (quite
> > a large part of the design).

>
> > A full Moore machine, all outputs driven by registers. In full custom
> > this allows the large IO pad drivers to provide the feedback. Much of
> > the instruction decode is pipelined due to most significant decoded
> > bits are in the low byte.

>
> > Should be suitable for interfacing to BRAM (with common address on
> > read and write) or external SRAM.

>
> > cheers jacko

>
> > p.s. much of the pipelining is only possible with a low logic area
> > because of the half width data bus dual fetching of data. Even though
> > the design is big endian, the fetches and stores are done little
> > endian for the usual carry propergation reasons, and for instruction
> > decode efficiency.

>
> goglecode?
>
> G-spot?
> have you ever found it?
>
> Antti


googlecode um yes my spelling is bad. nibzG.vhd is the filename..
Chrome doesn't (didn't) recognize the word as a spelling error. It's a
full Moore state machine now, with none of the Mealy race conditions.
In development Mealy is easier to flesh out a design to roughly
(ignoring race conditions not sure if state transition extra terms get
added automatically anyhow) do whats wanted. But in the end I had to
optimize it to a Moore machine with its greater performance. I hope
it's correct, but I have not built any IO yet to really test it. It
looks correct on the readings of the code. I haven't put any timing
constraints on it yet but speed could be raised. As 72MHz > 66MHz I
don't intend to do this yet.

unless a glaring error is found, this version will remain as the final
one to go toward the reference system.

cheers jacko
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  #4 (permalink)  
Old 05-21-2009, 09:52 PM
Jacko
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Posts: n/a
Default Re: Nibz VHDL Processor (Version G-spot)

I'm starting on the video.

-- The display
-- ===========
-- The generated vga mode is 640*480 pixels.
-- This is reduced with a border (black)
-- to 512*256. This is split into 1024
-- character cells of 16*8 pixels.
-- The character data starts at base address
-- $E000 and occupies the top 8K cells of
-- memory. As there are 8 lines per character
-- there is a possible 1024 character glyphs.

-- This allows full bit mapped graphics.
-- Each character is indirectly assigned via
-- the character code and colour table in
-- the lowest 1K cells of memory. It is
-- shadowed behind the boot ROM and is write
-- only. Each entry has the lower 10 bits as
-- a character index, and 6 high bits for
-- forground (15-13) and background (12-10)
-- colours. RGB bit order with R being most
-- significant.

-- A full decenders display can be made if
-- the display is turned on edge.

Sounds good to me, any comments?

cheers jacko
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  #5 (permalink)  
Old 05-21-2009, 10:31 PM
Jacko
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Posts: n/a
Default Re: Nibz VHDL Processor (Version G-spot)

I'm starting on the video.

-- The display
-- ===========
-- The generated vga mode is 640*480 pixels.
-- This is reduced with a border (black)
-- to 512*256. This is split into 1024
-- character cells of 16*8 pixels.
-- The character data starts at base address
-- $E000 and occupies the top 8K cells of
-- memory. As there are 8 lines per character
-- there is a possible 1024 character glyphs.

-- This allows full bit mapped graphics.
-- Each character is indirectly assigned via
-- the character code and colour table in
-- the lowest 1K cells of memory. It is
-- shadowed behind the boot ROM and is write
-- only. Each entry has the lower 10 bits as
-- a character index, and 6 high bits for
-- forground (15-13) and background (12-10)
-- colours. RGB bit order with R being most
-- significant.

-- A full decenders display can be made if
-- the display is turned on edge.

Sounds good to me, any comments? Maybe high to low index order of the
raster, so only 6.25MHz memory bandwidth used

cheers jacko
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  #6 (permalink)  
Old 05-22-2009, 06:19 AM
Guest
 
Posts: n/a
Default Re: Nibz VHDL Processor (Version G-spot)

On May 21, 11:31*pm, Jacko <[email protected]> wrote:
> I'm starting on the video.
>
> -- The display
> -- ===========
> -- The generated vga mode is 640*480 pixels.
> -- This is reduced with a border (black)
> -- to 512*256. This is split into 1024
> -- character cells of 16*8 pixels.
> -- The character data starts at base address
> -- $E000 and occupies the top 8K cells of
> -- memory. As there are 8 lines per character
> -- there is a possible 1024 character glyphs.
>
> -- This allows full bit mapped graphics.
> -- Each character is indirectly assigned via
> -- the character code and colour table in
> -- the lowest 1K cells of memory. It is
> -- shadowed behind the boot ROM and is write
> -- only. Each entry has the lower 10 bits as
> -- a character index, and 6 high bits for
> -- forground (15-13) and background (12-10)
> -- colours. RGB bit order with R being most
> -- significant.
>
> -- A full decenders display can be made if
> -- the display is turned on edge.
>
> Sounds good to me, any comments? Maybe high to low index order of the
> raster, so only 6.25MHz memory bandwidth used
>
> cheers jacko


Jack

once you start a video logical next steps are
2) release RECORD button
3) upload to youtube [optional]

are you still recording?
or what it is what you started?
if you started thinkig about adding video to nibz then why not stop
thinking and go on doing?

if something feels good to you then go ahead and and do it.
why do you need someone to tell you that?

FYI most people are used to count memory capacity in
bits or bytes, you are using "jacko cell's as measurement
unit this is not so well known, at least now

if you want comment on the new nibz:

1) MAX II is WAY too expensive for considering to be used for soft
processor, so it is totally nonsense targetting MAX II
2) a soft core optimized for MAX II makes little to none sense on any
other FPGA than MAX II

based on [1] and [2] you should get some decent FPGA board and make
some real processor that has real use also.
if you need some board, I would be happy to donate some.

sorry that i say what i think, some people do not appreciate it, but
it is what i think really
i tried to make soft core useable on MAX II - 240, but never fully
finished it, it may have been useful, as 240 is still cheap
but core that is useable in 1270 or 2220 makes no sense as the price
is not comparable any more.

I am doing something that is optimized for one FPGA as well, but i'd
say that makes sense in my case
the design AP32ACT is optimized for A3P060 and
1) is fully tested on target board
2) utilizes nearly 100% of _any_ type of resources available in that
FPGA
3) is supported by high level language compiler
4) has proven tested uart bootloader
5) has proven tested SD card bootloader
6) has several demos, interrupt handler, character LCD hello,..

funnily, I am thinking adding video too

but, I am not considering the AP32ACT to be used in any other FPGA
then the one it was originally targetted for,
because any other FPGA (i dont call MAX II FPGA, they are CPLDs') has
more resources useable and can use
more featured soft core

Antti








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  #7 (permalink)  
Old 05-22-2009, 09:44 AM
HT-Lab
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Posts: n/a
Default Re: Nibz VHDL Processor (Version G-spot)


<[email protected]> wrote in message
news:[email protected]...
On May 21, 5:26 pm, jacko <[email protected]> wrote:
>> Hi
>>
>> 72MHz it's hot! But cool. Lower un-necessary D_O pin state transitions
>> etc. Estimated 17 MIPS on 8 bit bus.

... snip
>
>goglecode?
>
>G-spot?
>have you ever found it?


Hahahaha, very good.....:-)

Hans
www.ht-lab.com


>
>Antti



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  #8 (permalink)  
Old 05-22-2009, 05:38 PM
jacko
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Posts: n/a
Default Re: Nibz VHDL Processor (Version G-spot)

As is it's fully device independent VHDL. UFM code not written
correctly yet.

> once you start a video logical next steps are
> 2) release RECORD button
> 3) upload to youtube [optional]


I will when I get that far.

> are you still recording?
> or what it is what you started?
> if you started thinkig about adding video to nibz then why not stop
> thinking and go on doing?


I was asking for commentary. I will be doing it quite soon. I was
wondering if suit a video mode would be the most logical.

> if something feels good to you then go ahead and and do it.
> why do you need someone to tell you that?
>
> FYI most people are used to count memory capacity in
> bits or bytes, you are using "jacko cell's as measurement
> unit this is not so well known, at least now
>
> if you want comment on the new nibz:
>
> 1) MAX II is WAY too expensive for considering to be used for soft
> processor, so it is totally nonsense targetting MAX II
> 2) a soft core optimized for MAX II makes little to none sense on any
> other FPGA than MAX II
>
> based on [1] and [2] you should get some decent FPGA board and make
> some real processor that has real use also.
> if you need some board, I would be happy to donate some.


When I run out of space on the 1270 I may take you up on that.

> sorry that i say what i think, some people do not appreciate it, but
> it is what i think really
> i tried to make soft core useable on MAX II - 240, but never fully
> finished it, it may have been useful, as 240 is still cheap
> but core that is useable in 1270 or 2220 makes no sense as the price
> is not comparable any more.


About 40 dollars. It is getting higher.

> I am doing something that is optimized for one FPGA as well, but i'd
> say that makes sense in my case
> the design AP32ACT is optimized for A3P060 and
> 1) is fully tested on target board
> 2) utilizes nearly 100% of _any_ type of resources available in that
> FPGA
> 3) is supported by high level language compiler
> 4) has proven tested uart bootloader
> 5) has proven tested SD card bootloader
> 6) has several demos, interrupt handler, character LCD hello,..


Cool.

> funnily, I am thinking adding video too


Cool.

> but, I am not considering the AP32ACT to be used in any other FPGA
> then the one it was originally targetted for,
> because any other FPGA (i dont call MAX II FPGA, they are CPLDs') has
> more resources useable and can use
> more featured soft core


Yes it is a CPLD, but the nibz is device independent so may be useful
for some FPGAs too. Especially if a large hardware thing needs a
little controller for some IO level management on the FPGA.

cheers jacko
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  #9 (permalink)  
Old 05-22-2009, 11:27 PM
Jacko
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Posts: n/a
Default Re: Nibz VHDL Processor (Version G-spot)

http://nibz.googlecode.com new vga.vhd download available. Hope it
helps you out at about 140 LEs.

Any comments welcome. Only supports a 512*256 sub pane, as the logic
is easier and has less demands on LEs. It does an indirection and so
the colour table only does 2 colours per 16*8 character location. Uses
8 bit data bus. Needs to be combined with a DMA control circuit. Doing
an 8*8 character format should be an easy enough conversion. The
default divider to get 25MHz pixel clock is from 66.0MHz but is
generic and accumulated to 11 bits precision.

The indexing down supports character data in high memory if the full
1024 characters are not needed. Now I'll need to make some 16 by 8
characters for a wide font. Or some common character pair compressed
font??

cheers jacko
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