FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal


Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 01-03-2004, 08:03 AM
Posts: n/a
Default Newbie Question: Compiling VHDL in Mentor Graphics

Hi all,

trying to get my head around mentor graphics. I have typed a bunch of code
and I am now trying to compile it. I am using Mentor Graphics.

Basically I go into the HDL designer window, set a root for my design and I
then click on the task manager icon which brings up a list of tasks for me
to carry out on the VHDL code. I click on 'Generate' which responds by
indicating 'Generation Completed Succesfully'. I then set the ModelSim
compile path to the following:


In that the above directory holds my vhdl files. I then click ModelSim
compile and I get the following response, which it pauses on:

Performing compile...
Library adaptive_encoder_transmitter_lib

Like I mentioned...this is as far as it goes. Looking at my CPU processes,
it doesn't actually seem to be doing anything.

Any ideas? Or is there some other way to get my vhdl files to compile? I am
using HDL Designer 2003.2.


- Kingsley

Reply With Quote


Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On

Similar Threads
Thread Thread Starter Forum Replies Last Post
Yet another newbie question lei Verilog 2 05-30-2008 01:05 AM
Another newbie question Howler Verilog 5 01-19-2005 09:54 PM

All times are GMT +1. The time now is 10:12 PM.

Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved