FPGA Groups

FPGA Groups (http://www.fpgacentral.com/group/index.php)
-   FPGA (http://www.fpgacentral.com/group/forumdisplay.php?f=14)
-   -   Net name convention for Xilinx UCF files. (http://www.fpgacentral.com/group/showthread.php?t=51018)

One Day & A Knight 12-23-2003 10:19 AM

Net name convention for Xilinx UCF files.
 
Hi, all:

I am writing some UCF files for synthesis. In XST I set the hierarchy
seperator to / and bus symbol to []...

Now after I write the UCF files and build, the ISE6.1 complain can't find
the net-names.

How do I find the correct names of the various symbols in my Verilog codes?
Is it possible to write a "netlist" in the NGC files?


Best Regards,
Kelvin




In core.v
Module main;

testctl u_testctrl(
...
.srck_i(p_srck_i), //testctrl input

.arstn_testrx_i(arstn_testrx), //testctrl input
.clk36_pll_i(clk_36), //testctrl input
);

....
endmodule

in core_ucf.ucf
NET "u_testctrl/clk36_pll_o" TNM_NET = "u_testctrl_clk36_pll_o";
TIMESPEC "TS_u_testctrl_clk36_pll_o" = PERIOD "u_testctrl_clk36_pll_o" 27.8
ns HIGH 50 %;


Error in core.bld
ERROR:NgdBuild:756 - Line 87 in core_ucf.ucf': Could not find net(s)
'u_testctrl/clk36_pll_i' in the design. To suppress this error specify
the
correct net name or remove the constraint.




Martin Euredjian 12-23-2003 03:23 PM

Re: Net name convention for Xilinx UCF files.
 
> How do I find the correct names of the various symbols in my Verilog
codes?
> Is it possible to write a "netlist" in the NGC files?


FPGA Editor helps. You can also use the Constraints Editor.

Also try: "*u_testctrl/clk36_pll_o"
instead of: "u_testctrl/clk36_pll_o"

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
[email protected]
where
"0_0_0_0_" = "martineu"





Muthu 12-23-2003 03:51 PM

Re: Net name convention for Xilinx UCF files.
 
"One Day & A Knight" <[email protected]> wrote in message news:<[email protected]>...
> Hi, all:
>
> I am writing some UCF files for synthesis. In XST I set the hierarchy
> seperator to / and bus symbol to []...
>
> Now after I write the UCF files and build, the ISE6.1 complain can't find
> the net-names.
>
> How do I find the correct names of the various symbols in my Verilog codes?
> Is it possible to write a "netlist" in the NGC files?
>
>
> Best Regards,
> Kelvin
>
>
>
>
> In core.v
> Module main;
>
> testctl u_testctrl(
> ...
> .srck_i(p_srck_i), //testctrl input
>
> .arstn_testrx_i(arstn_testrx), //testctrl input
> .clk36_pll_i(clk_36), //testctrl input
> );
>
> ...
> endmodule
>
> in core_ucf.ucf
> NET "u_testctrl/clk36_pll_o" TNM_NET = "u_testctrl_clk36_pll_o";
> TIMESPEC "TS_u_testctrl_clk36_pll_o" = PERIOD "u_testctrl_clk36_pll_o" 27.8
> ns HIGH 50 %;
>
>
> Error in core.bld
> ERROR:NgdBuild:756 - Line 87 in core_ucf.ucf': Could not find net(s)
> 'u_testctrl/clk36_pll_i' in the design. To suppress this error specify
> the
> correct net name or remove the constraint.


Hi,

Your .ucf having "pll_o" and ERROR shows "pll_i". I think you have
copied wrong lines. thats ok.

XST tools will not change the instance names during synthesis. so,
whatever you type in RTL should be valid in PAR too.

I am doubting, the hiearchy seperator only. Because, XST by default
takes "." as hiearchy seperator. Pls check that again, whether you
have forced correctly to "/"

and you can generate netlist after Translation phase.

it is "ngd2ver" application from Xilinx tools.

Get back for any clarification.

Regards,
Muthu

One Day & A Knight 12-24-2003 05:21 AM

Re: Net name convention for Xilinx UCF files.
 
Yeah, that is indeed a copy error.

Now I switch to a single "clk_36"...and it seemed to work. "clk_36" is an
implicitly defined wire label.

I do remember there is a document said all the names and definitions in the
source code will
remain unchanged, but how come it doesn't in my case.

In the source code, there is no simple *u_testctrl?clk36_pll_o. All I found
from the ngd2ver is a
totally new definition u_testctrl/Mmux_clk36_pll_o_Result1_1. This is quite
strange to me.

And I am sure there is no command called ngc2ver now.

Thank you Muthu and Martin.


Best Regards,
Kelvin





Muthu <[email protected]> wrote in message
news:[email protected] om...
> "One Day & A Knight" <[email protected]> wrote in message

news:<[email protected]>...
> > Hi, all:
> >
> > I am writing some UCF files for synthesis. In XST I set the hierarchy
> > seperator to / and bus symbol to []...
> >
> > Now after I write the UCF files and build, the ISE6.1 complain can't

find
> > the net-names.
> >
> > How do I find the correct names of the various symbols in my Verilog

codes?
> > Is it possible to write a "netlist" in the NGC files?
> >
> >
> > Best Regards,
> > Kelvin
> >
> >
> >
> >
> > In core.v
> > Module main;
> >
> > testctl u_testctrl(
> > ...
> > .srck_i(p_srck_i), //testctrl input
> >
> > .arstn_testrx_i(arstn_testrx), //testctrl input
> > .clk36_pll_i(clk_36), //testctrl input
> > );
> >
> > ...
> > endmodule
> >
> > in core_ucf.ucf
> > NET "u_testctrl/clk36_pll_o" TNM_NET = "u_testctrl_clk36_pll_o";
> > TIMESPEC "TS_u_testctrl_clk36_pll_o" = PERIOD "u_testctrl_clk36_pll_o"

27.8
> > ns HIGH 50 %;
> >
> >
> > Error in core.bld
> > ERROR:NgdBuild:756 - Line 87 in core_ucf.ucf': Could not find net(s)
> > 'u_testctrl/clk36_pll_i' in the design. To suppress this error

specify
> > the
> > correct net name or remove the constraint.

>
> Hi,
>
> Your .ucf having "pll_o" and ERROR shows "pll_i". I think you have
> copied wrong lines. thats ok.
>
> XST tools will not change the instance names during synthesis. so,
> whatever you type in RTL should be valid in PAR too.
>
> I am doubting, the hiearchy seperator only. Because, XST by default
> takes "." as hiearchy seperator. Pls check that again, whether you
> have forced correctly to "/"
>
> and you can generate netlist after Translation phase.
>
> it is "ngd2ver" application from Xilinx tools.
>
> Get back for any clarification.
>
> Regards,
> Muthu




PO Laprise 01-02-2004 05:33 PM

Re: Net name convention for Xilinx UCF files.
 
One Day & A Knight wrote:

> I do remember there is a document said all the names and definitions in the
> source code will
> remain unchanged, but how come it doesn't in my case.
>
> In the source code, there is no simple *u_testctrl?clk36_pll_o. All I found
> from the ngd2ver is a
> totally new definition u_testctrl/Mmux_clk36_pll_o_Result1_1. This is quite
> strange to me.


In my experience, the synthesis tools do a relatively good job of
keeping the net names, or something very close, but sometimes it just
isn't possible. Often, some nets are duplicates of other nets,
optimized out, merged, or G knows what else... Try to follow the
netlist logic to see whether this is truly the net that you want (you
should be able to tell by examining the other nets that join it to form
logic functions). Personally, I use X's constraints editor initially to
find the net, and then edit my UCF manually or with scripts. The
synthesis tools rarely cause me problems by spuriously changing net
names on me on subsequent syntheses barring major changes in my code.

--
Pierre-Olivier

-- to email me directly, remove all _N0SP4M_ from my address --



All times are GMT +1. The time now is 12:39 PM.

Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved