FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 03-02-2005, 03:34 PM
Guest
 
Posts: n/a
Default Need suggestion abt FFs without RST for pipelined datapath.

Hi all,
I am currently implementing a module which has large number of
registers(the datapath is heavily pipelined and lotsa registers). To
reduce the area of the design , I have replaced many of the internal
registers ,with FFs without a RESET pin.
So now all the internal register dont get cleared (reset) while
applying an external reset. they just keep on shifting unknown value,
until the actual data fills in the pipeline. this is perfectly
acceptable for me except for the initial X's I see in waveform, till
the actual data reaches to the point.

I save around 10-15% area by this way. (in a total size of ~90K).
My module is part of a ~1.5Mgates asic.

I want to ask you people , whether this method of reducing area will
cause any problems(in the design flow) considering the total system.

please giveme ur valuable suggestions.

thanks a lot
Deepu John

Reply With Quote
  #2 (permalink)  
Old 03-02-2005, 10:54 PM
J o h n _ E a t o n (at) hp . com (no spaces)
Guest
 
Posts: n/a
Default Re: Need suggestion abt FFs without RST for pipelined datapath.

[email protected] wrote:
> Hi all,
> I am currently implementing a module which has large number of
> registers(the datapath is heavily pipelined and lotsa registers). To
> reduce the area of the design , I have replaced many of the internal
> registers ,with FFs without a RESET pin.
> So now all the internal register dont get cleared (reset) while
> applying an external reset. they just keep on shifting unknown value,
> until the actual data fills in the pipeline. this is perfectly
> acceptable for me except for the initial X's I see in waveform, till
> the actual data reaches to the point.
>
> I save around 10-15% area by this way. (in a total size of ~90K).
> My module is part of a ~1.5Mgates asic.
>
> I want to ask you people , whether this method of reducing area will
> cause any problems(in the design flow) considering the total system.
>
> please giveme ur valuable suggestions.
>
> thanks a lot
> Deepu John
>


One problem can occur with back annotated gate sims. It is possible to
create logic that works but cannot be simulated unless you have a way
to initialize registers to a known value. (Anything but X).

But as you noticed it can be costly to put a reset on every flop in the
design. Not only is there an area cost but you have to route that reset
around the entire chip and meet setup/hold timing on every flop.

I like the idea of multicycle resets where you are required to hold a reset
for X number of cycles. Then as long as you can reset everything by cycle
X then everything will work.

John Eaton







Reply With Quote
  #3 (permalink)  
Old 03-02-2005, 11:49 PM
KCL
Guest
 
Posts: n/a
Default Re: Need suggestion abt FFs without RST for pipelined datapath.

For simulation probleme you could put a value to your signal when you
declare it
like:

signal temp : std_logic :='0';
like that it will have an initial value different from X at start but will
not be synthetized

Alexis

"J o h n _ E a t o n (at) hp . com (no spaces)" <"J o h n _ E a t o n (at)
hp . com (no spaces)"> a écrit dans le message de news:
[email protected]
> [email protected] wrote:
>> Hi all,
>> I am currently implementing a module which has large number of
>> registers(the datapath is heavily pipelined and lotsa registers). To
>> reduce the area of the design , I have replaced many of the internal
>> registers ,with FFs without a RESET pin.
>> So now all the internal register dont get cleared (reset) while
>> applying an external reset. they just keep on shifting unknown value,
>> until the actual data fills in the pipeline. this is perfectly
>> acceptable for me except for the initial X's I see in waveform, till
>> the actual data reaches to the point.
>>
>> I save around 10-15% area by this way. (in a total size of ~90K).
>> My module is part of a ~1.5Mgates asic.
>>
>> I want to ask you people , whether this method of reducing area will
>> cause any problems(in the design flow) considering the total system.
>>
>> please giveme ur valuable suggestions.
>>
>> thanks a lot
>> Deepu John
>>

>
> One problem can occur with back annotated gate sims. It is possible to
> create logic that works but cannot be simulated unless you have a way
> to initialize registers to a known value. (Anything but X).
>
> But as you noticed it can be costly to put a reset on every flop in the
> design. Not only is there an area cost but you have to route that reset
> around the entire chip and meet setup/hold timing on every flop.
>
> I like the idea of multicycle resets where you are required to hold a
> reset
> for X number of cycles. Then as long as you can reset everything by cycle
> X then everything will work.
>
> John Eaton
>
>
>
>
>
>
>



Reply With Quote
  #4 (permalink)  
Old 03-03-2005, 07:09 AM
nonoe
Guest
 
Posts: n/a
Default Re: Need suggestion abt FFs without RST for pipelined datapath.


"KCL" <[email protected]> wrote in message
news:[email protected]
> For simulation probleme you could put a value to your signal when you
> declare it
> like:
>
> signal temp : std_logic :='0';
> like that it will have an initial value different from X at start but will
> not be synthetized


Perhaps that works easily with VHDL, but many Verilog synthesis tools
may reject the equivalent:

reg q;

initial q = 1'b0; // for simulation-only!

.....
(or for a more modern Verilog-2001 tool)

reg q = 1'b0;


Reply With Quote
  #5 (permalink)  
Old 03-03-2005, 07:14 AM
Thomas Stanka
Guest
 
Posts: n/a
Default Re: Need suggestion abt FFs without RST for pipelined datapath.

Hi,

[email protected] wrote:
> reduce the area of the design , I have replaced many of the internal
> registers ,with FFs without a RESET pin.

[..]
> I want to ask you people , whether this method of reducing area will
> cause any problems(in the design flow) considering the total system.


If you insert these FF in a scan chain, you could not reset them.
I was told that this will be not acceptable for the ASIC vendor. Maybe you
should check the needs of your vendor.

bye Thomas

--
Emailantworten bitte an thomas[at]obige_domain.
Usenet_10 ist für Viren und Spam reserviert
Reply With Quote
  #6 (permalink)  
Old 03-03-2005, 03:45 PM
Ray Andraka
Guest
 
Posts: n/a
Default Re: Need suggestion abt FFs without RST for pipelined datapath.

[email protected] wrote:

>Hi all,
> I am currently implementing a module which has large number of
>registers(the datapath is heavily pipelined and lotsa registers). To
>reduce the area of the design , I have replaced many of the internal
>registers ,with FFs without a RESET pin.
>So now all the internal register dont get cleared (reset) while
>applying an external reset. they just keep on shifting unknown value,
>until the actual data fills in the pipeline. this is perfectly
>acceptable for me except for the initial X's I see in waveform, till
>the actual data reaches to the point.
>
>I save around 10-15% area by this way. (in a total size of ~90K).
>My module is part of a ~1.5Mgates asic.
>
>I want to ask you people , whether this method of reducing area will
>cause any problems(in the design flow) considering the total system.
>
>please giveme ur valuable suggestions.
>
>thanks a lot
>Deepu John
>
>
>

generally, it won't cause a problem except for with ASIC folks who don't
accept anything less than 100% reset. You can make the reset totally
invisible by a) making sure you break all internal loops by forcing a
reset on one element in the loop and holding that reset for enough
clocks to make the known data propagate all the way around the loop, and
b) putting reset on all the output registers that is applied immediately
and then held until good data propagates to the output register. The
output register reset can easily be accomplished by using a sync RS-FF
that is set by the reset input signal and then cleared by either a
delayed version of the input reset signal or using a counter that is
preset by the input reset signal and whose terminal count clears that
FF. Same is true for the loop resets.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email [email protected]
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759


Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
software suggestion needed mk Verilog 1 11-16-2005 10:32 AM
Need suggestion abt FFs without RST for pipelined datapath. [email protected] Verilog 5 03-03-2005 03:45 PM
Any suggestion for an IP project Ouadid FPGA 1 02-19-2005 09:48 PM
Virtex-4 suggestion: TSMCCCS change Allan Herriman FPGA 0 06-10-2004 12:22 PM


All times are GMT +1. The time now is 07:26 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved