FPGA Central

Hi,

I have some questions regarding the following piece of code...

In the AHDL code, the following variable is declared as below:

HDET_REG : DFF;

Its been used in the code as follows:

HDET_REG.CLK = DIGRESET;
HDET_REG.D = VCC;
HDET.REG.CLRN = !HDET;

My question is that....how does this DFF work

How does CLRN affect the output HDET_REG.Q

Any help is greatly appreciated.

Thank you,

Methi

Hi methi,

> HDET_REG : DFF;
>
> Its been used in the code as follows:
>
> HDET_REG.CLK = DIGRESET;
> HDET_REG.D = VCC;
> HDET.REG.CLRN = !HDET;

Firstly, I find this _ugly_.

What happens is that as long as HDET is 1, the Q output of this DFF remains
0. If HDET is 0, the DFF will be set to 1 on the next transition for
DIGRESET from 0 to 1. HDET has a higher priority then DIGRESET and is
asynchronous.

In VHDL you'd write this as

process(DIGRESET, HDET)
begin
if HDET = '1' then
HDET_REG <= '0';
elsif rising_edge(DIGRESET) then
HDET_REG <= '1';
end if;
end process;

Yuck...


Ben

Hi Ben,

Actually I am trying to figure out this AHDL code I have and hence
translate it into VHDL...

The part of the code , I am tryin to understand and hence implement in
VHDL is as follows:

IF PD[9..2] == H"FF" THEN
TRS0 = VCC;
ELSE TRS0 = GND;
END IF;


IF PD[9..2] == H"00" AND TRS0Q THEN
TRS1 = VCC;
ELSE TRS1 = GND;
END IF;


IF PD[9..2] == H"00" AND TRS1Q THEN
TRS2 = VCC;
ELSE TRS2 = GND;
END IF;



TRS0LATCH.CLK = PCLK_DIG;
TRS0LATCH.ENA = TRS0;
TRS0LATCH.D = TRS0;
TRS0LATCH.CLRN = TRSRESET;
TRS0Q = TRS0LATCH.Q;



TRS1LATCH.CLK = PCLK_DIG;
TRS1LATCH.ENA = TRS1;
TRS1LATCH.D = TRS1;
TRS1LATCH.CLRN = TRSRESET;
TRS1Q = TRS1LATCH.Q;


TRS2LATCH.CLK = PCLK_DIG;
TRS2LATCH.ENA = TRS2;
TRS2LATCH.D = TRS2;
TRS2LATCH.CLRN = TRSRESET;
TRS2Q = TRS2LATCH.Q;



IF TRS0Q & TRS1Q & TRS2Q THEN
XYZ = VCC;
ELSE XYZ = GND;
END IF;


XYZLATCH[].CLK = PCLK_DIG;
XYZLATCH[].ENA = XYZ;
XYZLATCH[2..0].D = PD[8..6];
XYZQ[] = XYZLATCH[].Q;



HSYNC = !XYZQ[0];
FIELD = !XYZQ[2];


TRESETGEN[].CLK = PCLK_DIG;
TRESETGEN[].D = TRESETGEN[].Q + 1;
TRESETGEN[].CLRN = TRSRESET;
TRESETGEN[].ENA = TRS0Q;
TCOUNT[] = TRESETGEN[].Q;

IF TCOUNT[] == H"3" THEN
TRSRESET = GND;
ELSE TRSRESET = VCC;
END IF;



GENHCOUNTER.CLOCK = PCLK_ANA;
GENHCOUNTER.SCLR = DIGHRESET;
GENCOUNT[] = GENHCOUNTER.Q[];

IF GENCOUNT[] == 2000 THEN
HDET = VCC;
ELSE HDET = GND;
END IF;

HDET_REG.CLK = DIGHRESET;
HDET_REG.D = VCC;
HDET_REG.CLRN = !HDET;

HSYNC_REG0.CLK = PCLK_DIG;
HSYNC_REG0.D = HSYNC;
HSYNC_REG1.CLK = PCLK_DIG;
HSYNC_REG1.D = HSYNC_REG0.Q;
HSYNC_PULSE = HSYNC_REG1.Q;
DIGHRESET = !HSYNC AND HSYNC_PULSE;




D_VIDEO_DET = !HDET_REG.Q;
DIG_VID_PRES = !HDET_REG.Q;



I hope that this is doing nothing but the work of some dflipflops and
counter...

Thank you,

Methi

Ben Twijnstra wrote:
> Hi methi,
>
> > HDET_REG : DFF;
> >
> > Its been used in the code as follows:
> >
> > HDET_REG.CLK = DIGRESET;
> > HDET_REG.D = VCC;
> > HDET.REG.CLRN = !HDET;
>
> Firstly, I find this _ugly_.
>
> What happens is that as long as HDET is 1, the Q output of this DFF remains
> 0. If HDET is 0, the DFF will be set to 1 on the next transition for
> DIGRESET from 0 to 1. HDET has a higher priority then DIGRESET and is
> asynchronous.
>
> In VHDL you'd write this as
>
> process(DIGRESET, HDET)
> begin
> if HDET = '1' then
> HDET_REG <= '0';
> elsif rising_edge(DIGRESET) then
> HDET_REG <= '1';
> end if;
> end process;
>
> Yuck...
>
>
> Ben