FPGA Central

I'm working on a project that needs four write ports in a number of
different register files. I'm already aware of time-multiplexing and
partitioning. Generating a flop-based register file would take far too
many resources.

Are there any other methods of implementing multiple write ports on a
single register file? Any nifty workarounds people have done? Any
paper ideas?

Luke wrote:
> I'm working on a project that needs four write ports in a number of
> different register files. I'm already aware of time-multiplexing and
> partitioning. Generating a flop-based register file would take far too
> many resources.
>
> Are there any other methods of implementing multiple write ports on a
> single register file? Any nifty workarounds people have done? Any
> paper ideas?

Google this group back a few weeks, the solution was presented in
detail to the exact same same question.

John Jakson

JJ wrote:
> Luke wrote:
>
>>I'm working on a project that needs four write ports in a number of
>>different register files. I'm already aware of time-multiplexing and
>>partitioning. Generating a flop-based register file would take far too
>>many resources.
>>
>>Are there any other methods of implementing multiple write ports on a
>>single register file? Any nifty workarounds people have done? Any
>>paper ideas?
>
>
> Google this group back a few weeks, the solution was presented in
> detail to the exact same same question.
>
> John Jakson

Bottom line: If you're using distributed memory (async read) rather than
BlockRAM style memory and don't want to time multiplex, you'll need 4
memories per independent port (4 write ports, one read -> 20 memories)
and as many XORs. Registers might not be so resource intensive after all.

Yeah, I looked into using that. It actually gets pretty expensive,
seems to have an exponential cost related to the number of write ports
for the XOR scheme. It is a very interesting solution though.

I have a multiple-port reorder buffer that uses partitioning to
implement multiple ports, which is very efficient. The reorder buffer
writes up to four entries at a time into the register file. So I'll
just use time-multiplexing for the register file and hide the extra
cycle of latency it takes to update the register file by keeping the
data in the reorder buffer an extra cycle.