FPGA Central

Hi,

I use Modelsim SE 6.0 simulator for my projects.
My Project is very big and it takes nearly 15 min for compilation.
As the license is network one, after compilation, it says simulation
license error - if license is not available. Is there a command
available in modelsim to check license on network?
Next, In my project only 3 to 4 files are changed frequently. Rest
other files are not disturbed at all.
But still I am recompiling all files. Are there any commands available
so that I can skip compiling files which are not changed at all?

Please help..

Regards,
JK

> Next, In my project only 3 to 4 files are changed frequently. Rest
> other files are not disturbed at all.
> But still I am recompiling all files. Are there any commands available
> so that I can skip compiling files which are not changed at all?
>
If you use Modelsim's project file you can simply right click and select
'Compile->Out of Date'. If not, then you need to use make.

KJ

>>
> If you use Modelsim's project file you can simply right click and select
> 'Compile->Out of Date'. If not, then you need to use make.
>
I'm using PE 5.8e and I just call VCOM from my editor to recompile the one
file I have edited, restart and ModelSim picks up the change just fine.
You see it saying "# Loading work.whatever"
/MikeJ

Hi JK,

<[email protected]> wrote in message
news:[email protected] ps.com...
> Hi,
>
> I use Modelsim SE 6.0 simulator for my projects.

Update to 6.1f if you can, 6.0 has some annoying GUI bugs.

> My Project is very big and it takes nearly 15 min for compilation.
> As the license is network one, after compilation, it says simulation
> license error - if license is not available. Is there a command
> available in modelsim to check license on network?

Sound like a network issue, you can issue "lmstat -f" to see how many
Modelsim licenses are available, perhaps they are all used? Under windows
(Dosbox/Cygwin) you need to change the command to "lmutil lmstat -f".

> Next, In my project only 3 to 4 files are changed frequently. Rest
> other files are not disturbed at all.
> But still I am recompiling all files. Are there any commands available
> so that I can skip compiling files which are not changed at all?

Yes, look in the manual for the vmake command.

Hans
www.ht-lab.com


>
> Please help..
>
> Regards,
> JK
>

[email protected] wrote:
> Hi,
>
> I use Modelsim SE 6.0 simulator for my projects.
> My Project is very big and it takes nearly 15 min for compilation.
> As the license is network one, after compilation, it says simulation
> license error - if license is not available. Is there a command
> available in modelsim to check license on network?
> Next, In my project only 3 to 4 files are changed frequently. Rest
> other files are not disturbed at all.
> But still I am recompiling all files. Are there any commands available
> so that I can skip compiling files which are not changed at all?
>
> Please help..
>
> Regards,
> JK
>


Hi there,

I guess you are trying to compile your design within
the Modelsim GUI (vsim), and then run the simulation.
Maybe it is better to separate it into two stages?

When you compile the verilog design, run vlog with -incr
option ("incremental").

When running vsim, if using VHDL, you can use -lic_vhdl,
and for verilog you can use -lic_vlog.

It might be useful to tell us
- which OS you are using?
- VHDL / verilog/ mix language
- how do you compiling the design? Within Modelsim GUI
or inside C-shell / Windows CMD?

In addition, is a lot of the design files you are compiling
are the xilinx / Altera libraries? If yes, you maybe able
to use library feature instead of compiling everything in
work. And the library will only need to be compiled once.

Joseph

Thank you all for your prompt replies.

@ Hans - Thank you - license command works - but MAKE always fail..
gives weird errors.

@ Joseph -
You are right - I am using Modelsim GUI for both compilation &
simulation.
Is it faster - compilation from command prompt??
Modelsim GUI uses a script file which consists of compilation order.
My project is having both Verilog & VHDL files - that is Mixed..
I am uisng Modelsim SE PLUS 6.0C - Linux OS.

Regards,
Krishna Janumanchi

>
> Hi there,
>
> I guess you are trying to compile your design within
> the Modelsim GUI (vsim), and then run the simulation.
> Maybe it is better to separate it into two stages?
>
> When you compile the verilog design, run vlog with -incr
> option ("incremental").
>
> When running vsim, if using VHDL, you can use -lic_vhdl,
> and for verilog you can use -lic_vlog.
>
> It might be useful to tell us
> - which OS you are using?
> - VHDL / verilog/ mix language
> - how do you compiling the design? Within Modelsim GUI
> or inside C-shell / Windows CMD?
>
> In addition, is a lot of the design files you are compiling
> are the xilinx / Altera libraries? If yes, you maybe able
> to use library feature instead of compiling everything in
> work. And the library will only need to be compiled once.
>
> Joseph

Thank you all for your prompt replies.

@ Hans - Thank you - license command works - but MAKE always fail..
gives weird errors.

@ Joseph -
You are right - I am using Modelsim GUI for both compilation &
simulation.
Is it faster - compilation from command prompt??
Modelsim GUI uses a script file which consists of compilation order.
My project is having both Verilog & VHDL files - that is Mixed..
I am uisng Modelsim SE PLUS 6.0C - Linux OS.

Regards,
Krishna Janumanchi

>
> Hi there,
>
> I guess you are trying to compile your design within
> the Modelsim GUI (vsim), and then run the simulation.
> Maybe it is better to separate it into two stages?
>
> When you compile the verilog design, run vlog with -incr
> option ("incremental").
>
> When running vsim, if using VHDL, you can use -lic_vhdl,
> and for verilog you can use -lic_vlog.
>
> It might be useful to tell us
> - which OS you are using?
> - VHDL / verilog/ mix language
> - how do you compiling the design? Within Modelsim GUI
> or inside C-shell / Windows CMD?
>
> In addition, is a lot of the design files you are compiling
> are the xilinx / Altera libraries? If yes, you maybe able
> to use library feature instead of compiling everything in
> work. And the library will only need to be compiled once.
>
> Joseph

[email protected] wrote:
> Thank you all for your prompt replies.
>
> @ Hans - Thank you - license command works - but MAKE always fail..
> gives weird errors.
>
> @ Joseph -
> You are right - I am using Modelsim GUI for both compilation &
> simulation.
> Is it faster - compilation from command prompt??
> Modelsim GUI uses a script file which consists of compilation order.
> My project is having both Verilog & VHDL files - that is Mixed..
> I am uisng Modelsim SE PLUS 6.0C - Linux OS.
>
> Regards,
> Krishna Janumanchi
>
>

Hi Krishna,

It won't be much faster, but by doing that you can avoid
your license problem.

Assumed your top level is "testbench". When you run (in Linux shell)

$> vsim -gui testbench

By default Modelsim will wait if the required license is not available,
and queue for a license. When the license is becoming available, it
will then start to load the design.

Another advantage of separating the compile stage is that you can
easily redirect stdout messages to a log file. And examine it if
things goes wrong. While inside the GUI, the console display inside
the GUI wondows will have limited number of text lines. Older error
or warning messages could be lost.

Joseph