FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 01-21-2004, 12:54 PM
samuel nobs
Guest
 
Posts: n/a
Default microblaze reg_addr and new_reg_value outputs

hello,

i am working with xilinx microblaze and i am trying to figure out the
purpose of the two undocumented output signals reg_addr (5 bits wide)
and new_reg_value (32 bits wide).

i assume that reg_addr outputs the register currently written to and
new_reg_value outputs the value written to this register.

is anyone able to confirm my assumptions?

thank you,
sam

Reply With Quote
  #2 (permalink)  
Old 01-21-2004, 02:00 PM
Goran Bilski
Guest
 
Posts: n/a
Default Re: microblaze reg_addr and new_reg_value outputs

Hi Sam,

Your assumption is correct.

The values is however only valid when the signal VALID_INSTR is '1'.
A write is also only happening when REG_WRITE is '1'.

The signal PC_EX is the instruction_address for the executing instruction
MSR_REG contains the current msr register value
PIPE_RUNNING is '1' when the pipeline is running ("no stalls")
INTERRUPT_TAKEN is '1' when an interrupt is acknowledge (when MicroBlaze
is jumping to the interrupt address)
JUMP_TAKEN is '1' when a jump is taken
PREFETCH_ADDR is showing how many instructions that has been prefetched
MB_Halted is '1' when MicroBlaze has been halted by the internal debug logic

Göran

samuel nobs wrote:

> hello,
>
> i am working with xilinx microblaze and i am trying to figure out the
> purpose of the two undocumented output signals reg_addr (5 bits wide)
> and new_reg_value (32 bits wide).
>
> i assume that reg_addr outputs the register currently written to and
> new_reg_value outputs the value written to this register.
>
> is anyone able to confirm my assumptions?
>
> thank you,
> sam
>


Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Registered Inputs and Outputs Speed Verilog 12 03-31-2008 08:52 AM
How to gnerate VCD file with hex outputs. vssumesh Verilog 3 02-18-2006 07:37 AM
regs outputs Bluedoze Verilog 1 01-26-2004 07:15 PM


All times are GMT +1. The time now is 07:55 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved