FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 11-21-2007, 12:22 PM
Ved
Guest
 
Posts: n/a
Default Measuring setup and hold time in Lab

Hi all,
How can we measure setup and hold time of a flip-flop on FPGA in lab ?

Regards,
Ved
Reply With Quote
  #2 (permalink)  
Old 11-21-2007, 03:00 PM
Guest
 
Posts: n/a
Default Re: Measuring setup and hold time in Lab

>How can we measure setup and hold time of a flip-flop on FPGA in lab ?

Short of sawing the top off the chip, you'll have to do it via the
pins, so you'll need to take into account propagation delays between
those pins and the logic element. Beyond that, the method is the
same. I assume you know how to do it for a "raw" flip-flop (like a
7474). There are integrated circuit devices designed to support such
measurements.

This is another "mystery" enquiry, which raises first the question
"Why would you want to do it anyway?" Do you want to measure "pin to
pin" behaviour or are you trying to measure the "real" behaviour
(whatever that means) of a logic element (whatever that means, given
that there may be no atomic component of the particular device which
could be described as a "flip-flop" until it's configured as part of
such a component by the design software).

For normal use of the device, you should just comply with the limits
shown in the data sheet. What you find may not apply to other devices
or under other operating conditions.
Reply With Quote
  #3 (permalink)  
Old 11-21-2007, 03:16 PM
John_H
Guest
 
Posts: n/a
Default Re: Measuring setup and hold time in Lab

Ved wrote:
> Hi all,
> How can we measure setup and hold time of a flip-flop on FPGA in lab ?
>
> Regards,
> Ved


Modern FPGAs don't have a setup *and* hold time for a single register.
The sample window for the FPGA is sub-picosecond.

Any measurements you try to make will be swamped by the system jitter of
your measurement setup leaving you with a statistical center and a wide
area around that center representing your system jitter.

Use the values provided by the manufacturer!

- John_H
Reply With Quote
  #4 (permalink)  
Old 11-21-2007, 04:27 PM
David Spencer
Guest
 
Posts: n/a
Default Re: Measuring setup and hold time in Lab


"Ved" <[email protected]> wrote in message
news:[email protected]m...
> Hi all,
> How can we measure setup and hold time of a flip-flop on FPGA in lab ?
>
> Regards,
> Ved


As others have suggested, the timing model of an FPGA is too complex for the
setup and hold requirements of a single flip-flop to have any significance
(or be measurable). The correct way to design an FPGA is define timing
constraints and then let the place and route tools achieve these. This way,
you are making the FPGA fit your requirements rather than making your design
work around the FPGA. All place and route tools also produce data-sheet type
reports that give pin-related timings.

If, for some academic reason, you did want to measure the characteristics of
a single flip-flop as seen at the device pins, who would need a trivial
design with clock and data inputs and a Q output. You drive the inputs from
a pulse generator that allows fine tuning of the delay between rising edges
and look at the output on a scope set to infinite persistence and triggered
by the clock input. You slide the data input edge with respect to the clock
until you start seeing the output stay low after the clock. (The clock
frequency needs to be twice the data frequency so that the flip-flop returns
low before the edge you are looking at.)


Reply With Quote
  #5 (permalink)  
Old 11-21-2007, 07:00 PM
Jim Granville
Guest
 
Posts: n/a
Default Re: Measuring setup and hold time in Lab

Ved wrote:
> Hi all,
> How can we measure setup and hold time of a flip-flop on FPGA in lab ?
>
> Regards,
> Ved


Because those are design limits, you cannot actually measure them
on a real device.
What you could derive in the lab, is the point in between these
values, where the actual sampling aperture sits.
Before that point, the FF captures the value, after that point
and it misses it.

It could be good educationally, to do this on (say) 8 FF's all
at the same time. ( 8 LEDS, or 16 leds to show two time-stamps ?)

I have thought that a sliding-contact on a stripline system
with CLK and DATA lines, could demonstrate well, as well as allow
very fine time adjustments.

Also provide fine adjustment on Vcc, and a can of Freeze,
and ask the students what happens then.

If you can vary very precisely in the time-domain, you could even
start to demonstrate meta-stable operation, but just showing the
variation in aperture times between those 8 FF's is enough of
a warning to students.

-jg

Reply With Quote
  #6 (permalink)  
Old 11-21-2007, 08:21 PM
David Spencer
Guest
 
Posts: n/a
Default Re: Measuring setup and hold time in Lab


"Jim Granville" <[email protected]> wrote in message
news:[email protected]
> Because those are design limits, you cannot actually measure them
> on a real device.
> What you could derive in the lab, is the point in between these
> values, where the actual sampling aperture sits.
> Before that point, the FF captures the value, after that point
> and it misses it.
>
> It could be good educationally, to do this on (say) 8 FF's all
> at the same time. ( 8 LEDS, or 16 leds to show two time-stamps ?)
>
> I have thought that a sliding-contact on a stripline system
> with CLK and DATA lines, could demonstrate well, as well as allow
> very fine time adjustments.
>
> Also provide fine adjustment on Vcc, and a can of Freeze,
> and ask the students what happens then.
>
> If you can vary very precisely in the time-domain, you could even
> start to demonstrate meta-stable operation, but just showing the
> variation in aperture times between those 8 FF's is enough of
> a warning to students.
>
> -jg
>

Howard Johnson has a setup that he uses at his high-speed design lectures to
demonstrate metastability. There are some details at:
http://www.sigcon.com/Pubs/news/4_4.htm, and more information in his first
book.


Reply With Quote
  #7 (permalink)  
Old 11-21-2007, 08:38 PM
Jim Granville
Guest
 
Posts: n/a
Default Re: Measuring setup and hold time in Lab

David Spencer wrote:
>
> Howard Johnson has a setup that he uses at his high-speed design lectures to
> demonstrate metastability. There are some details at:
> http://www.sigcon.com/Pubs/news/4_4.htm, and more information in his first
> book.


Yes, that is good, tho I see he is missing a R2 from the SCH, that is
referenced in the text. SCH as drawn would not work

-jg

Reply With Quote
  #8 (permalink)  
Old 11-25-2007, 10:04 AM
glen herrmannsfeldt
Guest
 
Posts: n/a
Default Re: Measuring setup and hold time in Lab

Ved wrote:

> How can we measure setup and hold time of a flip-flop on FPGA in lab ?


Configure a device with one FF connected to I/O pins. The clock likely
connects to a dedicated clock input pin. Put in signals with varying
delay and see what the output looks like.

As someone else mentioned, a stripline with a movable tap could
probably do it.

-- glen

Reply With Quote
  #9 (permalink)  
Old 11-25-2007, 05:44 PM
Peter Alfke
Guest
 
Posts: n/a
Default Re: Measuring setup and hold time in Lab

On Nov 21, 4:22 am, Ved <[email protected]> wrote:
> Hi all,
> How can we measure setup and hold time of a flip-flop on FPGA in lab ?


Ved,
1. Why do you want to do this? What do you gain?
2. The difference between set-up and hold time is a very small
fraction of a picosecond, for any given device and operating
condition.
3. Whatever you measure includes unknown clock delays and data delays,
so you really are not measuring the set-up time.
4. My advice: Measure performance and available speed margins by
implementing a shift register and increasing the clock rate until it
fails. Then you still do not know whether it failed because of clock-
to-Q, routing, or set-up time, but why would you care?

Peter Alfke, Xilinx Applications
Reply With Quote
  #10 (permalink)  
Old 11-26-2007, 09:08 PM
Mike Lewis
Guest
 
Posts: n/a
Default Re: Measuring setup and hold time in Lab


"glen herrmannsfeldt" <[email protected]> wrote in message
news[email protected] ..
> Ved wrote:
>
>> How can we measure setup and hold time of a flip-flop on FPGA in lab ?

>
> Configure a device with one FF connected to I/O pins. The clock likely
> connects to a dedicated clock input pin. Put in signals with varying
> delay and see what the output looks like.
>
> As someone else mentioned, a stripline with a movable tap could
> probably do it.
>
> -- glen
>


All of these ideas are measuring setup and hold of the FPGA (not the FF).

Mike


Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
FF setup and hold time. himassk FPGA 2 05-07-2007 06:19 PM
SETUP & HOLD time confusion M. Hamed FPGA 11 04-18-2007 12:35 AM
measure setup and hold time axr0284 FPGA 6 01-12-2007 01:08 PM
setup and hold time violations rsk Verilog 3 03-16-2005 06:09 PM
setup-hold time problems [email protected] FPGA 5 03-03-2005 07:46 AM


All times are GMT +1. The time now is 06:32 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved