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Old 01-16-2004, 04:07 PM
Brannon King
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Default mapper optimization

I've made an image illustrating a certain optimization that the VHDL/Verilog
compilers seem to make, but which the mapper does not seem to make. Can
someone explain why this is not done in the mapper?

Picture: http://www.starbridgesystems.com/ima...s/or_gates.png

The picture shows some linearly cascaded OR gates vs. a binary tree of OR
gates. The Xilinx Map/Par seem to have a much easier time with timing
constraints when the incoming file is organized binarily, yet it would seem
to me that would be an easy optimization for the mapper to perform.

What I want to do is use some 3rd-party EDIF generator tools and yet I'm
forced to manually tile out my gates binarily. Thoughts?


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Old 01-17-2004, 04:34 PM
Brian Drummond
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Default Re: mapper optimization

On 16 Jan 2004 11:07:19 EST, "Brannon King"
<[email protected]> wrote:

>I've made an image illustrating a certain optimization that the VHDL/Verilog
>compilers seem to make, but which the mapper does not seem to make. Can
>someone explain why this is not done in the mapper?
>
>Picture: http://www.starbridgesystems.com/ima...s/or_gates.png
>
>The picture shows some linearly cascaded OR gates vs. a binary tree of OR
>gates. The Xilinx Map/Par seem to have a much easier time with timing
>constraints when the incoming file is organized binarily, yet it would seem
>to me that would be an easy optimization for the mapper to perform.
>
>What I want to do is use some 3rd-party EDIF generator tools and yet I'm
>forced to manually tile out my gates binarily. Thoughts?
>

Consider using Leonardo Spectrum. I know it can read EDIF as well as
VHDL/Verilog, and see no reason why its optimisation tools can't be used
on a design read in from EDIF (though I've had no reason to try this
myself)

- Brian

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