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  #1 (permalink)  
Old 05-04-2006, 11:29 PM
nospam
Guest
 
Posts: n/a
Default LVDS inputs on Cyclone II


Some time ago I did some experimentation (for a very cost sensitive
application) with a Spartan 3 part using an LVDS differential input as a
voltage comparator for a crude delta sigma ADC.

The I/O bank Vcco was 3.3v the common mode on the LVDS inputs was half the
3.3v supply and the differential input voltage was (obviously) limited to
whatever it took drive the LVDS input one way or the other.

It worked fine.

Now the customer says he wants to use Cyclone II.

I want to run the I/O bank on 3.3v and for Cyclone II I don't want to have
to provide a 2.5v supply just for this one input.

So I ask an Altera FAE can I run an LVDS (as a crude voltage comparator)
input on 3.3v biased at 1.65v.

After an age I get the answer no, but I could use an LVPECL standard
<sigh>. Even from the very skimpy Altera data I can tell that 1.65v is
outside the LVPECL standard common mode range and LVPECL is only available
on dedicated clock input pins anyway.

So I ask the question again and after another age get told no, LVDS has to
run on 2.5v and no more than 650mV differential input with no further
explanation.

I just read through the Cyclone II Device Handbook again and find it says

"Cyclone II devices have one set of VCC pins (VCCINT) that power the
internal device logic array and input buffers that use the LVPECL, LVDS,
HSTL, or SSTL I/O standards."

So if I believe this the Vccio supply is irrelevant for LVDS receivers and
the FAE was talking crap again.

Can anyone confirm this and has anyone experience of using LVDS inputs as
voltage comparators on Cyclone II (or Spartan 3/3e for that matter).

--
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  #2 (permalink)  
Old 05-05-2006, 12:15 AM
Austin Lesea
Guest
 
Posts: n/a
Default Re: LVDS inputs on Cyclone II

nospam,

The LVDS input buffer in VII, II Pro, V4, Spartan 3, and 3E is a full
CMOS differential comparator, than will 'function' from rail to rail.

Basically, each input ties to both a nmos differential pair, AND a pmos
differential pair, so that even when one, or the other is cutoff (out of
its range), its complement is still in range, and will operate to sense
the difference properly.

Why did we go tothis extra trouble? Well, these are tiny devices, and
it basically costs nothing to do it right the first time, so that you
could meet or beat any standard that anyone dreams up without
redesigning it.

It is powered from Vccaux, not Vcco!

Since Vccaux is 2.5 volts in Spartan 3, that means that an input voltage
has to be in the range of 0 to 2.5 volts just to work at all (common
mode range). We don't specify it use at the rails, because we can't
cahracterize all the possible uses of the circuit. For low speeds, as I
said, it will function. Don't complain if it doesn't switch as fast as
it is specified for the LVDS specification (you are not using it there).

Since every IO pin also has a giant nmos and pmos stack for the single
ended driver attached to it, you also have a diode from ground to the
pins, and a diode to Vcco for the bank. That means if the pin voltage
tries to go below ground (negative ~ 0.5V or greater) or above Vcco
(~Vcco+~0.5V) you will clamp the pin to that one diode above or below
ground.

You should let the customer know who is likely to provide you with more
timely and useful information. They might change their mind....

Austin

nospam wrote:

> Some time ago I did some experimentation (for a very cost sensitive
> application) with a Spartan 3 part using an LVDS differential input as a
> voltage comparator for a crude delta sigma ADC.
>
> The I/O bank Vcco was 3.3v the common mode on the LVDS inputs was half the
> 3.3v supply and the differential input voltage was (obviously) limited to
> whatever it took drive the LVDS input one way or the other.
>
> It worked fine.
>
> Now the customer says he wants to use Cyclone II.
>
> I want to run the I/O bank on 3.3v and for Cyclone II I don't want to have
> to provide a 2.5v supply just for this one input.
>
> So I ask an Altera FAE can I run an LVDS (as a crude voltage comparator)
> input on 3.3v biased at 1.65v.
>
> After an age I get the answer no, but I could use an LVPECL standard
> <sigh>. Even from the very skimpy Altera data I can tell that 1.65v is
> outside the LVPECL standard common mode range and LVPECL is only available
> on dedicated clock input pins anyway.
>
> So I ask the question again and after another age get told no, LVDS has to
> run on 2.5v and no more than 650mV differential input with no further
> explanation.
>
> I just read through the Cyclone II Device Handbook again and find it says
>
> "Cyclone II devices have one set of VCC pins (VCCINT) that power the
> internal device logic array and input buffers that use the LVPECL, LVDS,
> HSTL, or SSTL I/O standards."
>
> So if I believe this the Vccio supply is irrelevant for LVDS receivers and
> the FAE was talking crap again.
>
> Can anyone confirm this and has anyone experience of using LVDS inputs as
> voltage comparators on Cyclone II (or Spartan 3/3e for that matter).
>
> --

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  #3 (permalink)  
Old 05-05-2006, 01:19 AM
Jim Granville
Guest
 
Posts: n/a
Default Re: LVDS inputs on Cyclone II

Austin Lesea wrote:
> nospam,
>
> The LVDS input buffer in VII, II Pro, V4, Spartan 3, and 3E is a full
> CMOS differential comparator, than will 'function' from rail to rail.
>
> Basically, each input ties to both a nmos differential pair, AND a pmos
> differential pair, so that even when one, or the other is cutoff (out of
> its range), its complement is still in range, and will operate to sense
> the difference properly.
>
> Why did we go tothis extra trouble? Well, these are tiny devices, and
> it basically costs nothing to do it right the first time, so that you
> could meet or beat any standard that anyone dreams up without
> redesigning it.
>
> It is powered from Vccaux, not Vcco!


Excellant and relevent info, I trust that this is all in the revised
data sheets ?

The 'better' LVDS devices offer rail-rail, but often specify a lower
speed, or Vos, outside the std 'sweet-spot'.

Most also have a small Hyst band - do the Xilinx ones ?


> Since Vccaux is 2.5 volts in Spartan 3, that means that an input voltage
> has to be in the range of 0 to 2.5 volts just to work at all (common
> mode range). We don't specify it use at the rails, because we can't
> cahracterize all the possible uses of the circuit. For low speeds, as I
> said, it will function. Don't complain if it doesn't switch as fast as
> it is specified for the LVDS specification (you are not using it there).
>
> Since every IO pin also has a giant nmos and pmos stack for the single
> ended driver attached to it, you also have a diode from ground to the
> pins, and a diode to Vcco for the bank. That means if the pin voltage
> tries to go below ground (negative ~ 0.5V or greater) or above Vcco
> (~Vcco+~0.5V) you will clamp the pin to that one diode above or below
> ground.
>
> You should let the customer know who is likely to provide you with more
> timely and useful information. They might change their mind....




-jg

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  #4 (permalink)  
Old 05-05-2006, 01:23 AM
Jim Granville
Guest
 
Posts: n/a
Default Re: LVDS inputs on Cyclone II

nospam wrote:

> Some time ago I did some experimentation (for a very cost sensitive
> application) with a Spartan 3 part using an LVDS differential input as a
> voltage comparator for a crude delta sigma ADC.
>
> The I/O bank Vcco was 3.3v the common mode on the LVDS inputs was half the
> 3.3v supply and the differential input voltage was (obviously) limited to
> whatever it took drive the LVDS input one way or the other.
>
> It worked fine.
>
> Now the customer says he wants to use Cyclone II.
>
> I want to run the I/O bank on 3.3v and for Cyclone II I don't want to have
> to provide a 2.5v supply just for this one input.
>
> So I ask an Altera FAE can I run an LVDS (as a crude voltage comparator)
> input on 3.3v biased at 1.65v.
>
> After an age I get the answer no, but I could use an LVPECL standard
> <sigh>. Even from the very skimpy Altera data I can tell that 1.65v is
> outside the LVPECL standard common mode range and LVPECL is only available
> on dedicated clock input pins anyway.
>
> So I ask the question again and after another age get told no, LVDS has to
> run on 2.5v and no more than 650mV differential input with no further
> explanation.


When someone says that, it starts to sniff of a back-back clamp diode
structure - some opamps do use this to protect sensistive 1st stage
devices. Would be surprising on a FPGA tho.

This is the sort of thing you could test on a bench very easily ?

-jg

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  #5 (permalink)  
Old 05-05-2006, 03:13 AM
Austin Lesea
Guest
 
Posts: n/a
Default Re: LVDS inputs on Cyclone II

jg,

If the part is hot socket capable (can plug in with power ON all IOs),
then the IO structure can't use the foundry self protecting IOs, and has
to use other tricks to meet ESD spec, and work. Back to back diodes are
pretty common.

As for seeing this sort of data in the spec sheet: I already said it
will not appear, as it is not a supported "use" (there is no standard
that requires it, and full support of any swing and common mode voltage
is crazy -- there would be a delay table for every Vcm and every swing).

If all you want is a reasonable comparator (which is basically faster
than any off the shelf comparator by a factor of hundreds to thousands),
it is there.

Austin

Jim Granville wrote:
> nospam wrote:
>
>> Some time ago I did some experimentation (for a very cost sensitive
>> application) with a Spartan 3 part using an LVDS differential input as a
>> voltage comparator for a crude delta sigma ADC.
>> The I/O bank Vcco was 3.3v the common mode on the LVDS inputs was half
>> the
>> 3.3v supply and the differential input voltage was (obviously) limited to
>> whatever it took drive the LVDS input one way or the other.
>> It worked fine.
>> Now the customer says he wants to use Cyclone II.
>> I want to run the I/O bank on 3.3v and for Cyclone II I don't want to
>> have
>> to provide a 2.5v supply just for this one input.
>> So I ask an Altera FAE can I run an LVDS (as a crude voltage comparator)
>> input on 3.3v biased at 1.65v.
>> After an age I get the answer no, but I could use an LVPECL standard
>> <sigh>. Even from the very skimpy Altera data I can tell that 1.65v is
>> outside the LVPECL standard common mode range and LVPECL is only
>> available
>> on dedicated clock input pins anyway.
>> So I ask the question again and after another age get told no, LVDS
>> has to
>> run on 2.5v and no more than 650mV differential input with no further
>> explanation.

>
>
> When someone says that, it starts to sniff of a back-back clamp diode
> structure - some opamps do use this to protect sensistive 1st stage
> devices. Would be surprising on a FPGA tho.
>
> This is the sort of thing you could test on a bench very easily ?
>
> -jg
>

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  #6 (permalink)  
Old 05-05-2006, 04:05 AM
nospam
Guest
 
Posts: n/a
Default Re: LVDS inputs on Cyclone II

Austin Lesea <[email protected]> wrote:

>It is powered from Vccaux, not Vcco!


Thanks for the insight. On the Spartan 3 initially I just ran the I/O bank
on 3.3v without worrying about it and it seemed to work. If the Spartan 3
data sheets says what the differential inputs are powered from I must have
missed it. The I/O pin schematic does show what Vcco is used for. I kinda
guessed the inputs ran from Vccaux although needing a Vccaux supply is a
minus point for the Spartan.

>Since Vccaux is 2.5 volts in Spartan 3, that means that an input voltage
>has to be in the range of 0 to 2.5 volts just to work at all (common
>mode range).


From memory the Cyclone II LVDS inputs have a similar common mode range so
if they really run from a 1.2v Vccint they must have a different
configuration and probably worse performance as a general purpose
comparator. Guess I'm going to have to experiment.
--
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  #7 (permalink)  
Old 05-05-2006, 04:25 AM
nospam
Guest
 
Posts: n/a
Default Re: LVDS inputs on Cyclone II

Jim Granville <[email protected]> wrote:

>> So I ask the question again and after another age get told no, LVDS has to
>> run on 2.5v and no more than 650mV differential input with no further
>> explanation.


> When someone says that, it starts to sniff of a back-back clamp diode
>structure - some opamps do use this to protect sensistive 1st stage
>devices. Would be surprising on a FPGA tho.


> This is the sort of thing you could test on a bench very easily ?


It wouldn't matter to me the converter keeps the comparator 1 'bit' either
side of it's switching point anyway.

Input offset and hysteresis will mess up the converter some, but I only
need 'crude'. When I was experimenting it was digitising an ac signal so I
couldn't easily make measurements. When I get back to it I will do some dc
testing and discover more about the comparator.

--
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  #8 (permalink)  
Old 05-05-2006, 04:26 AM
Jim Granville
Guest
 
Posts: n/a
Default Re: LVDS inputs on Cyclone II

Austin Lesea wrote:

> jg,
>
> If the part is hot socket capable (can plug in with power ON all IOs),
> then the IO structure can't use the foundry self protecting IOs, and has
> to use other tricks to meet ESD spec, and work. Back to back diodes are
> pretty common.


In FPGAs ? Can you give an example ?

>
> As for seeing this sort of data in the spec sheet: I already said it
> will not appear, as it is not a supported "use" (there is no standard
> that requires it, and full support of any swing and common mode voltage
> is crazy -- there would be a delay table for every Vcm and every swing).
>
> If all you want is a reasonable comparator (which is basically faster
> than any off the shelf comparator by a factor of hundreds to thousands),
> it is there.


Other vendors data sheets have items called 'Guaranteed by design' and
'not tested' - it tells designers what the limits of the device are.

This proves one _can_ publish usefull design info, and not have to add
any testing load to your flows. (which seems to be your aversion ? )

A LVDS cell is either rail-rail by design, or it is not. ( the good
ones are... )

-jg

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  #9 (permalink)  
Old 05-05-2006, 05:21 AM
Rob
Guest
 
Posts: n/a
Default Re: LVDS inputs on Cyclone II

> You should let the customer know who is likely to provide you with more
> timely and useful information. They might change their mind....


It depends where you are. Both companies have good and not so good FAE's.
But I believe it to be very important for a company to have good FAE's;
because sometimes it is the deciding factor as to which device an engineer
will pick.



"Austin Lesea" <[email protected]> wrote in message
news:[email protected]
> nospam,
>
> The LVDS input buffer in VII, II Pro, V4, Spartan 3, and 3E is a full CMOS
> differential comparator, than will 'function' from rail to rail.
>
> Basically, each input ties to both a nmos differential pair, AND a pmos
> differential pair, so that even when one, or the other is cutoff (out of
> its range), its complement is still in range, and will operate to sense
> the difference properly.
>
> Why did we go tothis extra trouble? Well, these are tiny devices, and it
> basically costs nothing to do it right the first time, so that you could
> meet or beat any standard that anyone dreams up without redesigning it.
>
> It is powered from Vccaux, not Vcco!
>
> Since Vccaux is 2.5 volts in Spartan 3, that means that an input voltage
> has to be in the range of 0 to 2.5 volts just to work at all (common mode
> range). We don't specify it use at the rails, because we can't
> cahracterize all the possible uses of the circuit. For low speeds, as I
> said, it will function. Don't complain if it doesn't switch as fast as it
> is specified for the LVDS specification (you are not using it there).
>
> Since every IO pin also has a giant nmos and pmos stack for the single
> ended driver attached to it, you also have a diode from ground to the
> pins, and a diode to Vcco for the bank. That means if the pin voltage
> tries to go below ground (negative ~ 0.5V or greater) or above Vcco
> (~Vcco+~0.5V) you will clamp the pin to that one diode above or below
> ground.
>
> You should let the customer know who is likely to provide you with more
> timely and useful information. They might change their mind....
>
> Austin
>
> nospam wrote:
>
>> Some time ago I did some experimentation (for a very cost sensitive
>> application) with a Spartan 3 part using an LVDS differential input as a
>> voltage comparator for a crude delta sigma ADC. The I/O bank Vcco was
>> 3.3v the common mode on the LVDS inputs was half the
>> 3.3v supply and the differential input voltage was (obviously) limited to
>> whatever it took drive the LVDS input one way or the other. It worked
>> fine. Now the customer says he wants to use Cyclone II. I want to run the
>> I/O bank on 3.3v and for Cyclone II I don't want to have
>> to provide a 2.5v supply just for this one input. So I ask an Altera FAE
>> can I run an LVDS (as a crude voltage comparator)
>> input on 3.3v biased at 1.65v. After an age I get the answer no, but I
>> could use an LVPECL standard
>> <sigh>. Even from the very skimpy Altera data I can tell that 1.65v is
>> outside the LVPECL standard common mode range and LVPECL is only
>> available
>> on dedicated clock input pins anyway. So I ask the question again and
>> after another age get told no, LVDS has to
>> run on 2.5v and no more than 650mV differential input with no further
>> explanation. I just read through the Cyclone II Device Handbook again and
>> find it says "Cyclone II devices have one set of VCC pins (VCCINT) that
>> power the
>> internal device logic array and input buffers that use the LVPECL, LVDS,
>> HSTL, or SSTL I/O standards."
>>
>> So if I believe this the Vccio supply is irrelevant for LVDS receivers
>> and
>> the FAE was talking crap again. Can anyone confirm this and has anyone
>> experience of using LVDS inputs as
>> voltage comparators on Cyclone II (or Spartan 3/3e for that matter). --



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  #10 (permalink)  
Old 05-05-2006, 05:27 AM
Rob
Guest
 
Posts: n/a
Default Re: LVDS inputs on Cyclone II

I did a design with a Cyclone (not CycloneII) where I received LVDS at
267Mbps while Vccio was powered with 3.3V. It wasn't clear in the data
sheet but I surmised it was possible from one of the Quartus reports. So I
checked with my FAE and he said it is possible to run the receivers at 3.3V,
but not the transmitters.

I've never used the CycloneII, but perhaps it is similar in this regard???



"nospam" <[email protected]> wrote in message
news:[email protected]
>
> Some time ago I did some experimentation (for a very cost sensitive
> application) with a Spartan 3 part using an LVDS differential input as a
> voltage comparator for a crude delta sigma ADC.
>
> The I/O bank Vcco was 3.3v the common mode on the LVDS inputs was half the
> 3.3v supply and the differential input voltage was (obviously) limited to
> whatever it took drive the LVDS input one way or the other.
>
> It worked fine.
>
> Now the customer says he wants to use Cyclone II.
>
> I want to run the I/O bank on 3.3v and for Cyclone II I don't want to have
> to provide a 2.5v supply just for this one input.
>
> So I ask an Altera FAE can I run an LVDS (as a crude voltage comparator)
> input on 3.3v biased at 1.65v.
>
> After an age I get the answer no, but I could use an LVPECL standard
> <sigh>. Even from the very skimpy Altera data I can tell that 1.65v is
> outside the LVPECL standard common mode range and LVPECL is only available
> on dedicated clock input pins anyway.
>
> So I ask the question again and after another age get told no, LVDS has to
> run on 2.5v and no more than 650mV differential input with no further
> explanation.
>
> I just read through the Cyclone II Device Handbook again and find it says
>
> "Cyclone II devices have one set of VCC pins (VCCINT) that power the
> internal device logic array and input buffers that use the LVPECL, LVDS,
> HSTL, or SSTL I/O standards."
>
> So if I believe this the Vccio supply is irrelevant for LVDS receivers and
> the FAE was talking crap again.
>
> Can anyone confirm this and has anyone experience of using LVDS inputs as
> voltage comparators on Cyclone II (or Spartan 3/3e for that matter).
>
> --



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  #11 (permalink)  
Old 05-05-2006, 07:54 AM
Bob
Guest
 
Posts: n/a
Default Re: LVDS inputs on Cyclone II


"Austin Lesea" <[email protected]> wrote in message
news:[email protected]
> nospam,
>
> The LVDS input buffer in VII, II Pro, V4, Spartan 3, and 3E is a full CMOS
> differential comparator, than will 'function' from rail to rail.
>
> Basically, each input ties to both a nmos differential pair, AND a pmos
> differential pair, so that even when one, or the other is cutoff (out of
> its range), its complement is still in range, and will operate to sense
> the difference properly.
>
> Why did we go tothis extra trouble? Well, these are tiny devices, and it
> basically costs nothing to do it right the first time, so that you could
> meet or beat any standard that anyone dreams up without redesigning it.
>
> It is powered from Vccaux, not Vcco!
>
> Since Vccaux is 2.5 volts in Spartan 3, that means that an input voltage
> has to be in the range of 0 to 2.5 volts just to work at all (common mode
> range). We don't specify it use at the rails, because we can't
> cahracterize all the possible uses of the circuit. For low speeds, as I
> said, it will function. Don't complain if it doesn't switch as fast as it
> is specified for the LVDS specification (you are not using it there).
>


[snip]

Austin,

Are you saying that, since in V2-V4 the LVDS input buffer is driven from
VCCAUX, even if a bank's VCCO is not 2.5V you may instantiate an LVDS25
input? What about an LVDS output in a non-2.5V VCCO bank?

Thanks much,
Bob


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  #12 (permalink)  
Old 05-05-2006, 11:59 AM
Symon
Guest
 
Posts: n/a
Default Re: LVDS inputs on Cyclone II

"Austin Lesea" <[email protected]> wrote in message
news:[email protected]
>
> As for seeing this sort of data in the spec sheet: I already said it will
> not appear, as it is not a supported "use" (there is no standard that
> requires it, and full support of any swing and common mode voltage is
> crazy -- there would be a delay table for every Vcm and every swing).
>
> If all you want is a reasonable comparator (which is basically faster than
> any off the shelf comparator by a factor of hundreds to thousands), it is
> there.
>
> Austin
>

Hi Austin,
I agree. It's also clear why this behaviour isn't published. I for one am
impressed with the performance and flexibility of the LVDS inputs, they've
eased my design problems considerably over the past few years. Good job.
Cheers, Syms.


p.s. Note I didn't even moan about how they're compromised at high
frequencies by the input capacitance. Oh bugger, I just did. ;-)


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  #13 (permalink)  
Old 05-05-2006, 04:34 PM
Austin Lesea
Guest
 
Posts: n/a
Default Re: LVDS inputs on Cyclone II

Bob,

There are some combinations that may be possible to set the config bits
to support, but we intentionally choose not to do so (no standard).

So, just because something is possible, does not mean we need to support it.


Safest thing to do here is to power Vcco from 2.5V, Vccaux is 2.5V, and
you instantiate a LVDS25 input.

If you instantiate a LVDS25 input and the Vcco is 3.3V, all you get is a
design rule error (3.3V and 2.5V IOs in same bank). If you can ignore
the error, and get a bitstream anyway, there you go (success).

Austin


> [snip]
>
> Austin,
>
> Are you saying that, since in V2-V4 the LVDS input buffer is driven from
> VCCAUX, even if a bank's VCCO is not 2.5V you may instantiate an LVDS25
> input? What about an LVDS output in a non-2.5V VCCO bank?
>
> Thanks much,
> Bob
>
>

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  #14 (permalink)  
Old 05-05-2006, 05:34 PM
Piotr Wyderski
Guest
 
Posts: n/a
Default Re: LVDS inputs on Cyclone II

nospam wrote:

> So I ask an Altera FAE can I run an LVDS (as a crude voltage comparator)
> input on 3.3v biased at 1.65v.
>
> After an age I get the answer no


Don't worry, the answer "no" is the safest possible answer, so it is
often used as the default reply. :-) Once I asked Cypress whether
I can do something fancy with their GPIF automaton and got the
answer "no". Then I sent the question again with more detailed info
and again received "no". Then I have created a prototype and
the "answer" from it was "oh, yes!". :-)

Rule of thumb: If FAE says "yes", then it "yes". If FAE says "no", then he
says.

> So I ask the question again and after another age get told no


Don't worry again, I still don't know whether I can temporarily deselect
a Spartan 3 device during reprogramming and grant the bus to another
DMA device... I bet the answer, if any, will be "no". :-)

Best regards
Piotr Wyderski

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  #15 (permalink)  
Old 05-05-2006, 10:44 PM
Ben Twijnstra
Guest
 
Posts: n/a
Default Re: LVDS inputs on Cyclone II

nospam wrote:

>
> Some time ago I did some experimentation (for a very cost sensitive
> application) with a Spartan 3 part using an LVDS differential input as a
> voltage comparator for a crude delta sigma ADC.
>
> The I/O bank Vcco was 3.3v the common mode on the LVDS inputs was half the
> 3.3v supply and the differential input voltage was (obviously) limited to
> whatever it took drive the LVDS input one way or the other.
>
> It worked fine.
>
> Now the customer says he wants to use Cyclone II.

....

> Can anyone confirm this and has anyone experience of using LVDS inputs as
> voltage comparators on Cyclone II (or Spartan 3/3e for that matter).


I have a bunch of Cyclone I and II designs using LVDS based at 1.65V that
are working just fine at 270MHz input rate. They are fed by either Gennum
9064 or CYV270M0101EQ cable equalizers (I prefer the Cypress, but it has
only just become available in volume).

I remember from my Altera days that there was some reference-ish design that
used the same trick to make an LVDS pair act as a Digta-Selma (or the other
way round) ADC. It had horrible DC properties, but at frequencies over
100Hz it was fairly accurate (16 bit up to 250KHz or so).

Best regards,


Ben

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