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  #1 (permalink)  
Old 10-01-2004, 05:33 PM
Martin Schoeberl
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Default JOP on Spartan-3 Starter Kit

I got the Spartan-3 Starter Kit yesterday from Xilinx. This board is a
really good bargain: A XC3S200 and 1MB SRAM for just $ 99,-. This board
makes it hard for guys like Tony Burch or me to sell FPGA boards ;-(
Only the Flash is a little bit small.... Not too much space left for
application data.

However, the board and the documentation is fine. It took me only half a
day to port JOP (a Java processor) from the Altera Cyclone to the Spartan
(thanks to Ed Anuff who did the hard part and wrote a memory generator
for Xilinx). Just two Xilinx specific files for the top-level and the
memory interface. You can find a Xilinx ISE project under xilinx/s3sk for
JOP on this board.

If you have such a board and want to try out JOP:

Download the JOP sources from: http://www.jopdesign.com/download.jsp
Compile the ISE project under ../xilinx/s3sk
Download JOP to the FPGA
Connect a serial cabel from your PC to the board
Open a command prompt in ../java/target
Change the COM-port in doit.bat
type: doit test test Clock

that's it, a small Java program should now run on the Spartan!

Martin
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/



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  #2 (permalink)  
Old 10-02-2004, 01:20 AM
Martin Schoeberl
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Default Re: JOP on Spartan-3 Starter Kit

> However, the board and the documentation is fine. It took me only half
a
> day to port JOP (a Java processor) from the Altera Cyclone to the

Spartan
> (thanks to Ed Anuff who did the hard part and wrote a memory generator
> for Xilinx). Just two Xilinx specific files for the top-level and the
> memory interface. You can find a Xilinx ISE project under xilinx/s3sk

for
> JOP on this board.
>


For those who are interested in a short comparison between Cyclone and
Spartan-3:

Cyclone EP1C6Q240C6:
fmax: 98 MHz, 2066 LC/Es (34% out of 5980)
Spartan-3 XC3S200-5
fmax: 82 MHz, 2015 LC/Es (52% out of 3840)

I mean a 4 input LUT with register for the LC/E comparison. The CLB or
slice numbers are just confusing. We can see that JOP needs about the
same resources in the A and X devices.
Both devices used are the fastest speed grade available. Is the Cyclone,
although 'older', faster than the Spartan-3?

It's interesting when we compare the two devices with respect to LC/Es
and memory (In case of memory I count K-Bytes (not bits) and don't care
about a 9th parity bit... Why do I need a parity bit for the block RAM?
Is there also a parity protection for the SRAM based configuration?):

XC3S50: 1536 LC/Es, 4*2KB=8KB, 4 HW multiplier
EP1C3: 2910 LC/Es, 13*0.5KB= 6.5KB
XC3S200: 3840 LC/Es, 12*2KB=24KB, 12 HW multiplier
EP1C4: 4000 LC/Es, 17*0.5KB= 8.5KB
EP1C6: 5980 LC/Es, 20*0.5KB= 10KB
XC3S400: 7168 LC/Es, 16*2KB=32KB, 16 HW multiplier
EP1C12: 12060 LC/Es, 52*0.5KB= 26KB
XC3S1000: 15360 LC/Es, 24*2KB=48KB, 24 HW multiplier
EP1C20: 20060 LC/Es, 64*0.5KB=32KB
XC3S1500: 26624 LC/Es, 32*2KB=64KB, 32 HW multiplier

When we order the parts with respect to LC/E count they alternate in a
nice way. Does that mean that our design complexity determines the
choice?
Not that easy. The X parts have more memory per LC and additional
multipliers. However, I don't have prices, a very important 'feature',
handy for all these devices :-)

Martin



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  #3 (permalink)  
Old 10-02-2004, 01:47 AM
Antti Karttunen (remove the trailing .do from the address)
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Default Capabilities of Spartan-3 Starter Kit (XC3S200).

Martin Schoeberl wrote:
> I got the Spartan-3 Starter Kit yesterday from Xilinx. This board is a
> really good bargain: A XC3S200 and 1MB SRAM for just $ 99,-. This board
> makes it hard for guys like Tony Burch or me to sell FPGA boards ;-(
> Only the Flash is a little bit small.... Not too much space left for
> application data. However, the board and the documentation is fine.
>


Good to know that people like it, because I'm
also "seriously buying" it!

However, being a complete newbie to FPGA's,
I would like to know what range of applications
this "DO-SPAR3-DK with XC3S200 FT256 Xilinx Spartan-3
FPGA" (just to make sure that we are speaking of
the same device!) is good for.

For example, at Xilinx's site there is a list
of various (mainly third party) processor cores,
starting from MC68000 and ending to Z80:
http://www.xilinx.com/xlnx/xebiz/sea...PProducts=Core

And for example, in CAST Inc.'s C68000's Data Sheet
http://www.xilinx.com/bvdocs/ipcente...AST_C68000.pdf
there is "Table 1: Example Implementation Statistics",
where the most low-end device listed is Spartan-IIE XC2S400E-7.

Does this mean that it is impossible to fit C68000
into XC3S200 which has only half of the system gates
of XC2S400E-7 ?
(I don't know whether the gate counts between
Spartan-IIE and Spartan-3 series compare linearly.)

Same problem with many other CAST's processor cores
mentioned: 80C51, TMS32025 and "Z80 Compatible Microprocessor"
CZ80CPU, the data sheets mention only Spartan-3 XC3S400-4 and
Spartan-IIE XC2S300E-7 and some larger Virtex-II's as Example
Devices on which to implement them.

Does this mean that XC3S200 has not enough logic
to implement ANY of these or just that CAST Inc.
didn't have XC3S200-device at hand, and thus
haven't tested their designs on it?

Also, most of the games and platforms mentioned at:
http://www.fpgaarcade.com/
seem to be implemented on at least 300K gate device.

So is this 200K-gate XC3S200 thus just a little bit
too small for them?

(Hmm... although on "Space Invaders" page:
http://home.freeuk.com/fpgaarcade/spc_main.htm
it mentions: "As so few of the available logic
elements are used, a much cheaper FPGA could be
used along with external memory device(s)."
So there is some hope.)

Also, one important question:
What is the maximum speed this XC3S200 can
be clocked with?


Yours,

Antti.
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  #4 (permalink)  
Old 10-02-2004, 01:59 AM
Martin Schoeberl
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Default Re: Capabilities of Spartan-3 Starter Kit (XC3S200).

> Good to know that people like it, because I'm
> also "seriously buying" it!


yes the board is cool, it's just incredible cheap...

> Does this mean that it is impossible to fit C68000
> into XC3S200 which has only half of the system gates
> of XC2S400E-7 ?
> (I don't know whether the gate counts between
> Spartan-IIE and Spartan-3 series compare linearly.)


The simplest way to check it out is to donwload Xilins ISE software (it's
free) and compile your design. You will see how it fit's and if there are
some resources left.

>
> Same problem with many other CAST's processor cores
> mentioned: 80C51, TMS32025 and "Z80 Compatible Microprocessor"
> CZ80CPU, the data sheets mention only Spartan-3 XC3S400-4 and
> Spartan-IIE XC2S300E-7 and some larger Virtex-II's as Example
> Devices on which to implement them.
>
> Does this mean that XC3S200 has not enough logic
> to implement ANY of these or just that CAST Inc.
> didn't have XC3S200-device at hand, and thus
> haven't tested their designs on it?


I expect the XC3S200 should do it, since I can easily fit a 32-bit CPU in
it.

> Also, one important question:
> What is the maximum speed this XC3S200 can
> be clocked with?


That depends really on your design. As above, run it through the (free)
synthesizer and you will get the numbers.

Martin


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  #5 (permalink)  
Old 10-02-2004, 02:57 AM
Steven K. Knapp
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Default Re: JOP on Spartan-3 Starter Kit


"Martin Schoeberl" <[email protected]> wrote in message
news:[email protected]

[snip]

> Both devices used are the fastest speed grade available. Is the Cyclone,
> although 'older', faster than the Spartan-3?


As a quick aside, Cyclone has three speed grades, Spartan-3 only two. In
general, a speed grade represents about a 15% difference in performance.

Slowest vs. slowest speed grade would be interesting.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC


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  #6 (permalink)  
Old 10-02-2004, 03:38 AM
Paul Leventis \(at home\)
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Default Re: JOP on Spartan-3 Starter Kit

Hi Martin,

> Cyclone EP1C6Q240C6:
> fmax: 98 MHz, 2066 LC/Es (34% out of 5980)
> Spartan-3 XC3S200-5
> fmax: 82 MHz, 2015 LC/Es (52% out of 3840)


By turning on Minimize Area w/Chains under Fitter Settings/More
Settings.../Auto Packed Registers - Cyclone you can cut the LE count to 1868
LEs (from 2066). Quartus doesn't try too hard to put registers & LUTs
together unless it runs out of room (or you tell it to with this setting).
In my compile, this didn't hurt Fmax (Fmax was 99 Mhz). On average,
aggressively packing can slightly hurt performance and cause an increase in
wiring.

By turning on "Area" mapping option in synthesis (instead of Balanced), this
drops further to 1775 LEs. Fmax = 95 Mhz.

Just pointing out that without even looking at the HDL, there are ways to
tweak the LE/Fmax trade-off. I'm sure there are some such tricks for Xilinx
too. To automatically try-out the area optimization tricks in Quartus, run
the Design Space Explorer tool, and select "Area Optimization" mode under
the Advanced settings. It'll take a while, but this will find you the best
settings (for area) for your design.

> Both devices used are the fastest speed grade available. Is the Cyclone,
> although 'older', faster than the Spartan-3?


Yes. This performance result is actually pretty poor as far as Cyclone vs.
Spartan-3 goes. We see an average of 80% better performance -- yes, that's
1.8X Fmax -- when comparing the fastest speed grades of the two chips with
default "push-button" results from Quartus & ISE over a suite of 49 designs.
Another way of looking at it is the slowest Cyclone speed-grade out-performs
the fastest Spartan-3 speed-grade by a considerable margin. See
http://www.altera.com/products/devic...ance_fpga.html
for details.

In this particular case, your critical path appears to stretch from a RAM to
a RAM (configured as a ROM) with little logic in-between. Logic +
routing-rich paths tend to accentuate the speed differences between the two
devices, while RAM-heavy paths show a smaller advantage.

> When we order the parts with respect to LC/E count they alternate in a
> nice way. Does that mean that our design complexity determines the
> choice?
> Not that easy. The X parts have more memory per LC and additional
> multipliers. However, I don't have prices, a very important 'feature',
> handy for all these devices :-)


And it also depends on which speedgrade you need to buy to meet your
performance -- can you get by with a slower speed-grade in Cyclone than
you'd need in Spartan-3? Or maybe with the faster Cyclone chips you may be
able to get away with a wider bus (less demultiplexing) resulting in fewer
LEs but a higher clock speed..

Picking a chip ain't easy... so just go with Altera ;-)

Regards,

Paul Leventis
Altera Corp.


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  #7 (permalink)  
Old 10-02-2004, 07:00 AM
Jim Granville
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Posts: n/a
Default Re: JOP on Spartan-3 Starter Kit

Paul Leventis (at home) wrote:

> Hi Martin,
>
>
>>Cyclone EP1C6Q240C6:
>> fmax: 98 MHz, 2066 LC/Es (34% out of 5980)
>>Spartan-3 XC3S200-5
>> fmax: 82 MHz, 2015 LC/Es (52% out of 3840)

>

<snip>
> To automatically try-out the area optimization tricks in Quartus, run
> the Design Space Explorer tool, and select "Area Optimization" mode under
> the Advanced settings. It'll take a while, but this will find you the best
> settings (for area) for your design.


Can you try that, and report back the speed gain, and how long it took
to find this ?
( IIRC you mentioned +37% in another post ?)

<snip>
> In this particular case, your critical path appears to stretch from a RAM to
> a RAM (configured as a ROM) with little logic in-between. Logic +
> routing-rich paths tend to accentuate the speed differences between the two
> devices, while RAM-heavy paths show a smaller advantage.


Do you have tips for Martin on how to improve this for Cyclone
specific cases ? - ie should the ROM change to logic-based, rather than
RAM based, or would a pipeline stage help ?

-jg

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  #8 (permalink)  
Old 10-02-2004, 07:19 AM
Hal Murray
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Default Re: JOP on Spartan-3 Starter Kit

> Why do I need a parity bit for the block RAM?

They are often useful for other things.

On FIFOs/buffers:
End of packet flag.
In-band vs out-of-band signaling.

Used/free flags.

Just plane more bits (wider) for things like table driven state machines.


--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

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  #9 (permalink)  
Old 10-02-2004, 12:01 PM
Martin Schoeberl
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Default Re: JOP on Spartan-3 Starter Kit

> > In this particular case, your critical path appears to stretch from a
RAM to
> > a RAM (configured as a ROM) with little logic in-between. Logic +
> > routing-rich paths tend to accentuate the speed differences between

the two
> > devices, while RAM-heavy paths show a smaller advantage.

>
> Do you have tips for Martin on how to improve this for Cyclone
> specific cases ? - ie should the ROM change to logic-based, rather than
> RAM based, or would a pipeline stage help ?
>

The critical path is from bytecode RAM (the instruction cache for the
processor), which has registered address but unregistered data ,out
through a 'larg' table. A jump table to map bytecode instructions to
microcode addresses. I was thinking to add another pipeline stage in this
path. However, than the bytecode branches take one more cycle.
When I add a register in this stage the critical path moved to the ALU
and fmax was 106MHz. Not a big win and it showed that the pipeline is not
so bad balanced.

If you have another good idea, I would be happy to make JOP faster :-)

Martin
--
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/



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  #10 (permalink)  
Old 10-02-2004, 06:03 PM
Martin Schoeberl
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Default Re: JOP on Spartan-3 Starter Kit

> As a quick aside, Cyclone has three speed grades, Spartan-3 only two.
In
> general, a speed grade represents about a 15% difference in

performance.
>
> Slowest vs. slowest speed grade would be interesting.


Ok, here it is:
Cyclone slowest (-8): 77.5MHz
Spartan slowest (-4): 77.8MHz
Looks now better for X....

And now let's throw in some price numbers. Prices are single units from
arrow.com and avnet.com, both devices in the same package (tqfp144):
Cyclone: EP1C6T144C6: $41.60
Cyclone: EP1C6T144C8: $27.70
Spartan-3: XC3S200-4TQ144C: $19.93
no price for -5 speed grade

And relate the price to density and speed in a 'funny' way:
price / 1000 LCs / MHz:

EP1C6-6: 41.60$ / 5.980 kLC / 98 MHz = 7.1 cent / kLC / MHz
EP1C6-8: 5.98 cent / kLC /MHz
XC3S200-T: $19.93 / 3.840 kLC / 77.8 MHz = 6.7 cent / kLC /MHz
and now it looks again better for A...

I did not take into account the multipliers and larger memories in the
Spartan, but also not the fact that the Cyclones are available for a
longer time (I got my first Cyclone samples 01/2003 and sold the first
boards 02/2003 :-)

Martin

--
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/




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  #11 (permalink)  
Old 10-02-2004, 06:32 PM
Sylvain Munaut
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Posts: n/a
Default Re: JOP on Spartan-3 Starter Kit


>>Slowest vs. slowest speed grade would be interesting.

>
> Ok, here it is:
> Cyclone slowest (-8): 77.5MHz
> Spartan slowest (-4): 77.8MHz
> Looks now better for X....


I can't reproduces those numbers ( or any of the one you gave ) (for xilinx, I mean, I don't have quartus installed),
how do you proceed exactly ?


> Spartan-3: XC3S200-4TQ144C: $19.93

Huh ? I can buy XC3S400-4FT256 for 23$ piece for very small qty (6 pieces in my case) and that's from an avnet company.


> And relate the price to density and speed in a 'funny' way:
> price / 1000 LCs / MHz:
>
> EP1C6-6: 41.60$ / 5.980 kLC / 98 MHz = 7.1 cent / kLC / MHz
> EP1C6-8: 5.98 cent / kLC /MHz
> XC3S200-T: $19.93 / 3.840 kLC / 77.8 MHz = 6.7 cent / kLC /MHz
> and now it looks again better for A...


For the XC3S400-4FT256 (assuming same frequency) : $23 / 7.680 kLC / 77.8Mhz = 3.85 cent / kLC / Mhz

Numbers ... you can make them tell anything you want


> I did not take into account the multipliers and larger memories in the
> Spartan, but also not the fact that the Cyclones are available for a
> longer time (I got my first Cyclone samples 01/2003 and sold the first
> boards 02/2003 :-)


Yup, I think there are 200LC used for a booth multiplier, should be easy to lower that with a dedicated multiplier (and also go faster i would guess).



Btw, is there any networking available ?
I have a Avnet Spartan 3 kit with an ethernet PHY on bard, that would be nice to get TCP/IP


Sylvain
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  #12 (permalink)  
Old 10-02-2004, 07:34 PM
E.S.
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Default Re: JOP on Spartan-3 Starter Kit

Martin Schoeberl wrote:

> For those who are interested in a short comparison between Cyclone and
> Spartan-3:
>
> Cyclone EP1C6Q240C6:
> fmax: 98 MHz, 2066 LC/Es (34% out of 5980)
> Spartan-3 XC3S200-5
> fmax: 82 MHz, 2015 LC/Es (52% out of 3840)


Where did you get this numbers from ?
I get on ISE 6.2.03:
xc3s200-4 Minimum period: 10.428ns (Maximum Frequency: 95.896MHz)
xc3s200-5 Minimum period: 9.503ns (Maximum Frequency: 105.235MHz)

cheers


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  #13 (permalink)  
Old 10-02-2004, 07:38 PM
Martin Schoeberl
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Default Re: JOP on Spartan-3 Starter Kit

Sylvain,

> >>Slowest vs. slowest speed grade would be interesting.

> >
> > Ok, here it is:
> > Cyclone slowest (-8): 77.5MHz
> > Spartan slowest (-4): 77.8MHz
> > Looks now better for X....

>
> I can't reproduces those numbers ( or any of the one you gave ) (for

xilinx, I mean, I don't have quartus installed),
> how do you proceed exactly ?


Set a time constraint for clk (in this case I used 12ns). However, this
should already be done in the UCF you downloaded with the project. Then
look at the 'text-based post-plcae & route static timing report'. At the
end you will find:

Design statistics:
Minimum period: 12.848ns (Maximum frequency: 77.833MHz)

Don't let yourself be fooled by the maximum frequency from the synthesis
report. These are dummy numbers (in this case 96 MHz...).

> > Spartan-3: XC3S200-4TQ144C: $19.93

> Huh ? I can buy XC3S400-4FT256 for 23$ piece for very small qty (6

pieces in my case) and that's from an avnet company.

The list price for the XC3S400-5FT256C (they don't have the -4 on the
website) at avnet.com is $41. I just compared the prices that are
available 'online'. I also got the Cyclone (Q240 package) cheaper: EUR
22.75 instead of $ ??..... for this device there is a 'call for quote' at
arrow.com. The lead free costs $32.90, but these are more expensive in
general.

Btw, does somebody know why the lead free devices are more expensive. I
did'n know up to now that semiconductors contain lead. I only know that
it's part of the solder and when it's forbidden will probably increase
production cost of PCBs.

> > I did not take into account the multipliers and larger memories in

the
> > Spartan, but also not the fact that the Cyclones are available for a
> > longer time (I got my first Cyclone samples 01/2003 and sold the

first
> > boards 02/2003 :-)

>
> Yup, I think there are 200LC used for a booth multiplier, should be

easy to lower that with a dedicated multiplier (and also go faster i
would guess).

Yes that would drop the LC count and I could go with the next smaller
Spartan-3. Uups, where is the XC3S100?
The multiplication would be faster, but the multiplication (imul bytecode
in the JVM) has a dynamic instruction frequency of 0.24% in typicall Java
programs. That would not compensate for the clock frequency factor of 1.2
between the Cyclone and the Spartan-3.

> Btw, is there any networking available ?
> I have a Avnet Spartan 3 kit with an ethernet PHY on bard, that would

be nice to get TCP/IP

Do you mean available with JOP? Yes, I have a small TCP/IP stack in Java
with drivers for the CS8900 (Ethernet), PPP and SLIP. Even a small
webserver is running on JOP: http://84.112.19.23 ;-)

Martin
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/



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  #14 (permalink)  
Old 10-02-2004, 07:44 PM
Martin Schoeberl
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Posts: n/a
Default Re: JOP on Spartan-3 Starter Kit

> Martin Schoeberl wrote:
>
> > For those who are interested in a short comparison between Cyclone

and
> > Spartan-3:
> >
> > Cyclone EP1C6Q240C6:
> > fmax: 98 MHz, 2066 LC/Es (34% out of 5980)
> > Spartan-3 XC3S200-5
> > fmax: 82 MHz, 2015 LC/Es (52% out of 3840)

>
> Where did you get this numbers from ?
> I get on ISE 6.2.03:
> xc3s200-4 Minimum period: 10.428ns (Maximum Frequency: 95.896MHz)
> xc3s200-5 Minimum period: 9.503ns (Maximum Frequency: 105.235MHz)
>

Don't take the numbers from the Synthesizer! Use the frequency after P&R,
in the post P&R static timing report.
This mistake is done by many ISE users. Xilinx should change the text in
the synthesizer report to state it clearly that this number is an
estimation!

Martin


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  #15 (permalink)  
Old 10-02-2004, 08:14 PM
Martin Schoeberl
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Default Re: JOP on Spartan-3 Starter Kit

Hi Paul,

> > Cyclone EP1C6Q240C6:
> > fmax: 98 MHz, 2066 LC/Es (34% out of 5980)
> > Spartan-3 XC3S200-5
> > fmax: 82 MHz, 2015 LC/Es (52% out of 3840)

>
> By turning on Minimize Area w/Chains under Fitter Settings/More
> Settings.../Auto Packed Registers - Cyclone you can cut the LE count to

1868
> LEs (from 2066). Quartus doesn't try too hard to put registers & LUTs
> together unless it runs out of room (or you tell it to with this

setting).
> In my compile, this didn't hurt Fmax (Fmax was 99 Mhz). On average,
> aggressively packing can slightly hurt performance and cause an

increase in
> wiring.


Thank's for the hint. It's nice to get it smaller AND faster.

> too. To automatically try-out the area optimization tricks in Quartus,

run
> the Design Space Explorer tool, and select "Area Optimization" mode

under
> the Advanced settings. It'll take a while, but this will find you the

best
> settings (for area) for your design.


I could not find the 'Design Space Explorer' in Quartus. If you mean the
Resource/Timeing Opt. Adviser under 'Tools' than I'm in bad luck. This
function is not available with the web edition of Quartus.

> In this particular case, your critical path appears to stretch from a

RAM to
> a RAM (configured as a ROM) with little logic in-between. Logic +
> routing-rich paths tend to accentuate the speed differences between the

two
> devices, while RAM-heavy paths show a smaller advantage.
>


In this case I think it's a logic/routing-rich path. From the memory data
out (unregistered) there is a 8-bit 'lookup table' and an adder,
resulting in 6 LCs till the next register (in this case the address
register of another RAM). Perhaps the ALM structure from the Stratix II
would help for this function, but the Stratix devices are too big and too
expensive ;-)
Or a clock-free ROM as it was available in the ACEX parts. In fact,
Quartus implements this structure in a block RAM when targeting the ACEX
device (I still have several ACEX boards laying around and collectiong
dust ;-).

Martin
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/



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  #16 (permalink)  
Old 10-02-2004, 08:59 PM
Martin Schoeberl
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Posts: n/a
Default Re: Capabilities of Spartan-3 Starter Kit (XC3S200).

> Same problem with many other CAST's processor cores
> mentioned: 80C51, TMS32025 and "Z80 Compatible Microprocessor"
> CZ80CPU, the data sheets mention only Spartan-3 XC3S400-4 and
> Spartan-IIE XC2S300E-7 and some larger Virtex-II's as Example
> Devices on which to implement them.
>
> Does this mean that XC3S200 has not enough logic
> to implement ANY of these or just that CAST Inc.
> didn't have XC3S200-device at hand, and thus
> haven't tested their designs on it?


You can find a 6809 with VGA, UART and keyboard controller running on the
Starter Kit at:
http://members.optushome.com.au/jeke...an3/index.html

Martin


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  #17 (permalink)  
Old 10-02-2004, 10:45 PM
Sylvain Munaut
Guest
 
Posts: n/a
Default Re: JOP on Spartan-3 Starter Kit


> Set a time constraint for clk (in this case I used 12ns). However, this
> should already be done in the UCF you downloaded with the project. Then
> look at the 'text-based post-plcae & route static timing report'. At the
> end you will find:
>
> Design statistics:
> Minimum period: 12.848ns (Maximum frequency: 77.833MHz)


Design statistics:
Minimum period: 17.812ns (Maximum frequency: 56.142MHz)

.... Even with effort level high, it's even worse !?

Design statistics:
Minimum period: 18.508ns (Maximum frequency: 54.031MHz)


Could you send me the exact files you compile to '246tnt' at the domaim gmail dot com ?
Maybe ise just don't like vmware ?


> Don't let yourself be fooled by the maximum frequency from the synthesis
> report. These are dummy numbers (in this case 96 MHz...).


Yup, I know that the warning is pretty clear

--- QUOTE ---
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
------------


> Btw, does somebody know why the lead free devices are more expensive. I
> did'n know up to now that semiconductors contain lead. I only know that
> it's part of the solder and when it's forbidden will probably increase
> production cost of PCBs.


The alloid used are more complex and uses more precious metals. (for
the solder balls and solder plating of terminal)
Sn/Pb before
and now, like Nickel/Palladium


>>Yup, I think there are 200LC used for a booth multiplier, should be

> easy to lower that with a dedicated multiplier (and also go faster i
> would guess).
>
> Yes that would drop the LC count and I could go with the next smaller
> Spartan-3. Uups, where is the XC3S100?


I'm more interested on the space I win to put more devices connected to
JOP like an ethernet mac, a i2s master, lcd controller ...

> The multiplication would be faster, but the multiplication (imul bytecode
> in the JVM) has a dynamic instruction frequency of 0.24% in typicall Java
> programs. That would not compensate for the clock frequency factor of 1.2
> between the Cyclone and the Spartan-3.


Sure, I never meant it would fill the gap !

>>Btw, is there any networking available ?
>>I have a Avnet Spartan 3 kit with an ethernet PHY on bard, that would

> be nice to get TCP/IP
>
> Do you mean available with JOP? Yes, I have a small TCP/IP stack in Java
> with drivers for the CS8900 (Ethernet), PPP and SLIP. Even a small
> webserver is running on JOP: http://84.112.19.23 ;-)


Silly me ... I must had a windows over my browser hiding the link
Since you use an external ethernet controller, I guess I would need a MAC
inside the FPGA and the appropriate drivers for it too.


Sylvain
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  #18 (permalink)  
Old 10-02-2004, 11:40 PM
Martin Schoeberl
Guest
 
Posts: n/a
Default Re: JOP on Spartan-3 Starter Kit

> > Set a time constraint for clk (in this case I used 12ns). However,
this
> > should already be done in the UCF you downloaded with the project.

Then
> > look at the 'text-based post-plcae & route static timing report'. At

the
> > end you will find:
> >
> > Design statistics:
> > Minimum period: 12.848ns (Maximum frequency: 77.833MHz)

>
> Design statistics:
> Minimum period: 17.812ns (Maximum frequency: 56.142MHz)


That's strange, perhaps you have a different version (my ISE is 6.2 as
shipped with the board).

> Could you send me the exact files you compile to '246tnt' at the domaim

gmail dot com ?
> Maybe ise just don't like vmware ?

done

> Yup, I know that the warning is pretty clear
>
> --- QUOTE ---
> NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
> FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
> GENERATED AFTER PLACE-and-ROUTE.
> ------------


Ooh, I'm sorry that I did not read it and complained about missing it in
another thread. One excuse: I usually don't read the synthesis results,
only the P&R reports. I only had to post about it since I get many of
these high fmax reports from Xilinx users (and this was an issue in the
MB thread too).

> The alloid used are more complex and uses more precious metals. (for
> the solder balls and solder plating of terminal)
> Sn/Pb before
> and now, like Nickel/Palladium


Solder balls ok, but that difference in QFP packages?

> > Do you mean available with JOP? Yes, I have a small TCP/IP stack in

Java
> > with drivers for the CS8900 (Ethernet), PPP and SLIP. Even a small
> > webserver is running on JOP: http://84.112.19.23 ;-)

>
> Silly me ... I must had a windows over my browser hiding the link
> Since you use an external ethernet controller, I guess I would need a

MAC
> inside the FPGA and the appropriate drivers for it too.


But a MAC is a big and difficult beast and you still need an external
chip for the voltage levels. An external Ethernet chip is cheap, works an
d you usually get a lot of memory for buffering Ethernet frames.

Martin
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/



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  #19 (permalink)  
Old 10-03-2004, 12:58 AM
Sylvain Munaut
Guest
 
Posts: n/a
Default Re: JOP on Spartan-3 Starter Kit


Hi Martin


> That's strange, perhaps you have a different version (my ISE is 6.2 as
> shipped with the board).


Thanks for the files.
I finally got to the same result. The problem was :
- A ISE 6.2 not updated
- A 'bad' constraint file



>>The alloid used are more complex and uses more precious metals. (for
>>the solder balls and solder plating of terminal)
>>Sn/Pb before
>>and now, like Nickel/Palladium

>
> Solder balls ok, but that difference in QFP packages?


I think the pins are plated with something similar to the solder to get good solering.
That plating probably must be "updated". Reflow temp is also higher IIRC


> But a MAC is a big and difficult beast and you still need an external
> chip for the voltage levels. An external Ethernet chip is cheap, works an
> d you usually get a lot of memory for buffering Ethernet frames.


Yeah but the devboard I have already has the PHY. (Standard Avnet spartan 3 kit).
But indeed the MAC seems pretty big ;( about 2000 slice.



Sylvain
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  #20 (permalink)  
Old 10-03-2004, 01:12 AM
Jim Granville
Guest
 
Posts: n/a
Default Re: JOP on Spartan-3 Starter Kit

Martin Schoeberl wrote:
> Btw, does somebody know why the lead free devices are more expensive. I
> did'n know up to now that semiconductors contain lead. I only know that
> it's part of the solder and when it's forbidden will probably increase
> production cost of PCBs.
>>The alloid used are more complex and uses more precious metals. (for
>>the solder balls and solder plating of terminal)
>>Sn/Pb before
>>and now, like Nickel/Palladium

>
>
> Solder balls ok, but that difference in QFP packages?


That's an easy one : because they can.
It's a good place to do a little cost recovery/price racking,
as users will have designed in the devices, and are thus captive
by both the legistation and the layout, plus many do not
compare Pb/PbFree prices, so that's the ideal time to nudge the
prices!

-jg

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  #21 (permalink)  
Old 10-03-2004, 05:12 AM
Subroto Datta
Guest
 
Posts: n/a
Default Re: JOP on Spartan-3 Starter Kit


"Martin Schoeberl" <[email protected]> wrote in message
news:[email protected]

>
> I could not find the 'Design Space Explorer' in Quartus. If you mean the
> Resource/Timeing Opt. Adviser under 'Tools' than I'm in bad luck. This
> function is not available with the web edition of Quartus.
>


Hi Martin,

The easiest way to use the DSE is to go the project directory, and type
1. quartus_sh --dse

If you want help on this feature type
2. quartus_sh --help=dse

Please make sure that the quartus\bin is in your path.

Additional information is available in the Quartus handbook at
http://www.altera.com/literature/hb/...s_qii52008.pdf

Here is the header from the help when you type in quartus_sh --help=dse




THE ALTERA DESIGN SPACE EXPLORER (DSE)



The Design Space Explorer (DSE) is a tool for exploring the

complex flow parameters in the Quartus(R) II software. DSE takes

the "guess work" out of selecting parameter values and exposes

the optimal Quartus II software settings for a design.



VERSION



2.1



SYNOPSIS



Usage: quartus_sh --dse [options]



Options:

-nogui

-project <project name>

-revision <revision name>

-seeds <seed list>

-llr-restructuring

-exploration-space <space>

-optimization-goal <goal>

-search-method <method>

-custom-file <filename>

-stop-after-gain <stop-after-gain value>

-stop-after-time <stop-after-time value>

-ignore-failed-base

-archive

-run-assembler

-slaves <slave list>

-use-lsf

-slack-column <column name>

-help



Note: To use DSE in command-line mode, specify the "-nogui"

option. If you do not specify this option, the DSE graphical

user interface (GUI) starts, regardless of the other

command-line options used.



EXAMPLES



quartus_sh --dse

This command launches the DSE GUI.



quartus_sh --dse -nogui -project main

This command starts a default command-line exploration. The

default seeds are used along with the default exploration

space, optimization goal, and search method.



quartus_sh --dse -nogui -project main -seeds 2,4,8-10

-exploration-space "Extra Effort Search"



This command starts a command-line exploration of an

"Extra Effort Search" space using the seeds 2, 4, 8

through 10, the default optimization goal, and the default

search method.



..............................

Hope this helps.

Subroto Datta
Altera Corp.


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  #22 (permalink)  
Old 10-04-2004, 01:29 AM
Antti Karttunen (remove the trailing .do from the address)
Guest
 
Posts: n/a
Default Differences between Xilinx ISE Foundation and WebPACK.

Martin Schoeberl wrote:
>
> You can find a 6809 with VGA, UART and keyboard controller running on the
> Starter Kit at:
> http://members.optushome.com.au/jeke...an3/index.html
>
> Martin


Thanks!
(so I guess similar 8-bit processors should
be on its limits.)

Here follows more newbie-questions.

As the Spartan-3 Starter Kit comes with only sixty
days evaluation version of "ISE Foundation", and
not time-limited version of "ISE WebPACK", I listed
their differences from http://www.xilinx.com/ise/devsys_feature_guide.pdf

and realized that WebPACK is lacking at least
these features that come with the Foundation:

CORE Generator System
Modular Design
FPGA Editor with Probe
SMARTModels for PowerPC and RocketIO.

What are these, and how essential they are
if I (eventually/immediately) want to do my own designs?

Also, does WebPACK support both VHDL and Verilog
fully?

Anybody knows if there there plans to port it (WebPACK)
to Linux or other Unix-systems, and when?
(And similar question for Altera's Quartus-II software.)


Yours,

Antti
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  #23 (permalink)  
Old 10-04-2004, 10:11 AM
Martin Schoeberl
Guest
 
Posts: n/a
Default Re: Differences between Xilinx ISE Foundation and WebPACK.

> What are these, and how essential they are
> if I (eventually/immediately) want to do my own designs?
>

Not very essential. You can do a lot with the free versions of ISE and
Quartus. All work I've done so far also compiles on the free Quartus
version (I have little experience on the ISE).
E.g. You don't need CoreGen to use the BRAM in the devices. It makes it
simpler, but you can instantiate these blocks with straight VHDL. See as
an example JOP that compiles from the plain VHDL sources on the free
versions of Xilinxs ISE and Alteras Quartus.

Martin
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/



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  #24 (permalink)  
Old 10-04-2004, 10:57 PM
Steven K. Knapp
Guest
 
Posts: n/a
Default Re: JOP on Spartan-3 Starter Kit


"Paul Leventis (at home)" <[email protected]> wrote in message
news:[email protected]

> Hi Martin,

[snip]
>
> > Both devices used are the fastest speed grade available. Is the Cyclone,
> > although 'older', faster than the Spartan-3?

>
> Yes. This performance result is actually pretty poor as far as Cyclone

vs.
> Spartan-3 goes. We see an average of 80% better performance -- yes,

that's
> 1.8X Fmax -- when comparing the fastest speed grades of the two chips with
> default "push-button" results from Quartus & ISE over a suite of 49

designs.
> Another way of looking at it is the slowest Cyclone speed-grade

out-performs
> the fastest Spartan-3 speed-grade by a considerable margin. See
>

http://www.altera.com/products/devic...ance_fpga.html
> for details.


Danger, Danger, Will Robinson, my B.S. sensors have detected significant
marketing content. :-)

As made famous by Philip Freidin (www.fliptronics.com), "There are four
kinds of lies.

1. Lies
2. Damn lies
3. Statistics
4. Benchmarks <--- *****

and in a category all by themselves, 'expense reports'".

Like Altera, Xilinx marketing has a benchmark suite showing that Spartan-3
performs better than Cyclone (shocking, I know). My own personal suite uses
more typical customer designs and shows a healthy mix of wins and losses,
very much depending on the characteristics of the design.

If Cyclone were _really_ 80% faster on _average_ than Spartan-3 comparing
fastest to fastest speed grades, do you _really_ think that this real-world
customer design, using out-of-the-box, default "push-button" settings, is
all that pathological? The two out-of-the-box results were roughly the same
when you compare the slowest speed grades for each family.

Cyclone -8 speed grade (slowest speed grade): 77.5 MHz
Spartan-3 -4 speed grade (slowest speed grade): 77.8 MHz

This is further borne out when you consider that Xilinx chose to have only
two speed grades for Spartan-3. For Xilinx devices, a speed grade
represents about a 15% speed difference.

Cyclone -6 speed grade (fastest of 3 speed grades): 98 MHz
Spartan-3 -5 speed grade (fastest of 2 speed grades): 82 MHz
15% over Spartan-3 -5 would result in 96.5 MHz

The comments about tweaking the default settings is very appropriate.
Changing a few of the default settings can have dramatic effect. Likewise,
small changes in coding can shave a layer or two of logic in a critical
clock path.

We cover some of these techniques at the upcoming Programmable World seminar
series. (Danger, danger, Marketing content follows!)

Programmable World 2004
http://www.xilinx.com/events/pw2004/

In specific, check out Workshop 3 in the Logic track.

Workshop 3: Spartan-3 and Low-Cost FPGA Design Techniques.
http://www.xilinx.com/events/pw2004/tracks/logic.htm
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC







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  #25 (permalink)  
Old 10-04-2004, 11:04 PM
Steven K. Knapp
Guest
 
Posts: n/a
Default Re: JOP on Spartan-3 Starter Kit


"Martin Schoeberl" <[email protected]> wrote in message
news:[email protected]
> > As a quick aside, Cyclone has three speed grades, Spartan-3 only two.

> In
> > general, a speed grade represents about a 15% difference in

> performance.
> >
> > Slowest vs. slowest speed grade would be interesting.

>
> Ok, here it is:
> Cyclone slowest (-8): 77.5MHz
> Spartan slowest (-4): 77.8MHz
> Looks now better for X....


Thank you. The results were about what I expected.

> And now let's throw in some price numbers. Prices are single units from
> arrow.com and avnet.com, both devices in the same package (tqfp144):
> Cyclone: EP1C6T144C6: $41.60
> Cyclone: EP1C6T144C8: $27.70
> Spartan-3: XC3S200-4TQ144C: $19.93
> no price for -5 speed grade
>
> And relate the price to density and speed in a 'funny' way:
> price / 1000 LCs / MHz:
>
> EP1C6-6: 41.60$ / 5.980 kLC / 98 MHz = 7.1 cent / kLC / MHz
> EP1C6-8: 5.98 cent / kLC /MHz
> XC3S200-T: $19.93 / 3.840 kLC / 77.8 MHz = 6.7 cent / kLC /MHz
> and now it looks again better for A...


[snip]

Be careful with this kind of analysis. Yes, it's helpful from an academic
point. However, the Spartan-3 XC3S1000 offers a sweet spot on cost per
logic cell. Does this mean that everyone should use the XC3S1000 when a
smaller part will do? No, you want to choose the lowest cost part that gets
the job done.

BTW, nice job on the Java processor! Very cool.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC


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