FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 11-16-2007, 10:15 AM
Toni Merwec
Guest
 
Posts: n/a
Default jitter-sensitive multi-output clk distribution for multi-gigabit-transceivers

Hi there,

I am currently designing an FPGA board, featuring two Xilinx Virtex-4 FPGAs.
I've already posted another question concerning a correct JTAG chain
implementation a few days ago and gained pretty good response. But some
problems remain... although on another topic:

I'll be using the Xilinx Virtex-4 FX series FPGAs featuring the high-speed
MGTs. The MGTs are located in two rows on each FPGA, each requiring their
own MGT reference clock, i.e. four reference clock inputs have to be fed
altogether plus at least one additional clock input for the core logic per
FPGA. Because the FPGAs have to exchange data synchronously (via the
standard GPIOs) I thought about using the same reference clocks for both
FPGA and making them the same as the MGT reference. Unfortunately that leads
to a clock signal that has to be distributed to at least 6 FPGA clock
inputs.

I don't think that a regular low-jitter clock device (and it HAS to be
low-jitter as for the reference for the MGTs) can drive 6 inputs over
several centimeters. I already used the ICS843020 clock synthesizer in
several other projects and wanted to use it again. Reason for the ICS is
that it features a programmable output frequency in the range of 35 - 700
MHz. Problem is, the ICS843020 has only two outputs. The Epson EG2121CA
device that is proposed in the Virtex-4 MGT user guide is not suitable
because these devices are restricted to one fixed frequency.

Maybe a clock buffer or multi-output clock distribution device is the
solution here, but I am afraid every additional device in the clock network
would introduce additional jitter which is the most critical aspect in this
application. Therefore I woul prefer a solution without those kind of
devices... if possible.

Has anyone ever had a similar problem and knows about an adequate solution?
Any help (if possible) is much appreciated. Thanks!

Regards Toni



Reply With Quote
  #2 (permalink)  
Old 11-16-2007, 11:49 AM
Philip Herzog
Guest
 
Posts: n/a
Default Re: jitter-sensitive multi-output clk distribution for multi-gigabit-transceivers

Toni Merwec wrote:
> Has anyone ever had a similar problem and knows about an adequate solution?


I don't know if this meets the jitter precision you need, but we're
using the following setup for 66MHz fpga-fpga communication here:

First FPGA gets an external clock, synchronizes its internal clock to
this via DCM.

Second DCM in first FPGA outputs the clock to a pin, pin is fed back to
another pin that is fed back into DCM-> clock on pin is synchronous to
internal clock.

Second FPGA gets clock from first FPGA, synchronizes its internal clock
to this via DCM.

HTH,

- Philip
--
Weisheit wird mit Löffeln gefressen. Manche Leute
benutzen eine Gabel...


Reply With Quote
  #3 (permalink)  
Old 11-16-2007, 06:10 PM
Guest
 
Posts: n/a
Default Re: jitter-sensitive multi-output clk distribution formulti-gigabit-transceivers

On Nov 16, 11:15 am, "Toni Merwec" <[email protected]> wrote:
> Hi there,
>
> I am currently designing an FPGA board, featuring two Xilinx Virtex-4 FPGAs.
> I've already posted another question concerning a correct JTAG chain
> implementation a few days ago and gained pretty good response. But some
> problems remain... although on another topic:
>
> I'll be using the Xilinx Virtex-4 FX series FPGAs featuring the high-speed
> MGTs. The MGTs are located in two rows on each FPGA, each requiring their
> own MGT reference clock, i.e. four reference clock inputs have to be fed
> altogether plus at least one additional clock input for the core logic per
> FPGA. Because the FPGAs have to exchange data synchronously (via the
> standard GPIOs) I thought about using the same reference clocks for both
> FPGA and making them the same as the MGT reference. Unfortunately that leads
> to a clock signal that has to be distributed to at least 6 FPGA clock
> inputs.
>
> I don't think that a regular low-jitter clock device (and it HAS to be
> low-jitter as for the reference for the MGTs) can drive 6 inputs over
> several centimeters. I already used the ICS843020 clock synthesizer in
> several other projects and wanted to use it again. Reason for the ICS is
> that it features a programmable output frequency in the range of 35 - 700
> MHz. Problem is, the ICS843020 has only two outputs. The Epson EG2121CA
> device that is proposed in the Virtex-4 MGT user guide is not suitable
> because these devices are restricted to one fixed frequency.
>
> Maybe a clock buffer or multi-output clock distribution device is the
> solution here, but I am afraid every additional device in the clock network
> would introduce additional jitter which is the most critical aspect in this
> application. Therefore I woul prefer a solution without those kind of
> devices... if possible.


http://www.onsemi.com/pub/Collateral/MC100EP210S-D.PDF

ON semiconductor list some 272 clock buffers - this is one of them.

--
Bill Sloman, Nijmegen
Reply With Quote
  #4 (permalink)  
Old 11-16-2007, 07:41 PM
Symon
Guest
 
Posts: n/a
Default Re: jitter-sensitive multi-output clk distribution for multi-gigabit-transceivers

"Toni Merwec" <[email protected]> wrote in message
news:[email protected]
>
> I'll be using the Xilinx Virtex-4 FX series FPGAs featuring the high-speed
> MGTs. Unfortunately that leads to a clock signal that has to be
> distributed to at least 6 FPGA clock inputs.
>
> I don't think that a regular low-jitter clock device (and it HAS to be
> low-jitter as for the reference for the MGTs) can drive 6 inputs over
> several centimeters. I already used the ICS843020 clock synthesizer in
> several other projects and wanted to use it again. Reason for the ICS is
> that it features a programmable output frequency in the range of 35 - 700
> MHz.
> Maybe a clock buffer or multi-output clock distribution device is the
> solution here, but I am afraid every additional device in the clock
> network would introduce additional jitter which is the most critical
> aspect in this application. Therefore I woul prefer a solution without
> those kind of devices... if possible.
>

Hi Toni,
A proper clock distribution device will introduce very little jitter. Use
some thing like this:-
http://www.micrel.com/_PDF/HBW/sy89832u.pdf

Filter its supplies properly.

HTH., Syms.


Reply With Quote
  #5 (permalink)  
Old 11-16-2007, 08:03 PM
Patrick Dubois
Guest
 
Posts: n/a
Default Re: jitter-sensitive multi-output clk distribution formulti-gigabit-transceivers

On 16 nov, 05:15, "Toni Merwec" <[email protected]> wrote:
>
> I don't think that a regular low-jitter clock device (and it HAS to be
> low-jitter as for the reference for the MGTs) can drive 6 inputs over
> several centimeters. I already used the ICS843020 clock synthesizer in
> several other projects and wanted to use it again. Reason for the ICS is
> that it features a programmable output frequency in the range of 35 - 700
> MHz. Problem is, the ICS843020 has only two outputs. The Epson EG2121CA
> device that is proposed in the Virtex-4 MGT user guide is not suitable
> because these devices are restricted to one fixed frequency.


Check out ICS843001-21:
http://www.xilinx.com/products/board...s843001-21.pdf

It's a frequency synthesizer with very low jitter. It's used on Xilinx
ML505 board for RocketIOs. Then I'm pretty sure that you can find a
low skew clock buffer to drive your 6 clocks.

Patrick
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Xilinx ISE + Multi CPU setup? [email protected] FPGA 5 07-03-2007 03:59 PM
Is this Multi-Cycle Path ? Ved FPGA 1 01-10-2007 10:41 PM
Multi place and route nezhate FPGA 3 06-06-2006 06:04 AM
Verifying multi-cyclicity of multi-cycle paths PO Laprise FPGA 1 04-02-2004 09:57 PM


All times are GMT +1. The time now is 04:22 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved