FPGA Central

Hi,

I have a simple question about memory organization. I would like to
write a memory controller for IS61LV25616AL SRAM (256K x 16) but I am
having trouble understanding how the memory organization works.

Datasheet says the memory is organized as 262,144 words by 16 bits
which is 256K x 16 but what does that mean in terms of rows and
columns ?

Is there a memory tutorial that someone can point me to ? or maybe a
memory controller that someone has written for an SRAM ?

Thanks,

On Mar 15, 9:11 am, ertw <[email protected]> wrote:
> Hi,
>
> I have a simple question about memory organization. I would like to
> write a memory controller for IS61LV25616AL SRAM (256K x 16) but I am
> having trouble understanding how the memory organization works.
>
> Datasheet says the memory is organized as 262,144 words by 16 bits
> which is 256K x 16 but what does that mean in terms of rows and
> columns ?
>
> Is there a memory tutorial that someone can point me to ? or maybe a
> memory controller that someone has written for an SRAM ?
>
> Thanks,

That's an SRAM, not an SDRAM. There are exactly as many address lines
as required to address 256k locations. It also doesn't appear to be
pipelined, so you just need to make sure that your controller meets
the setup & hold requirements of the part, and registers the read data
at the appropriate time.