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  #1 (permalink)  
Old 05-20-2006, 01:21 AM
bart
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Default ispLEVER Starter 6.0 FPGA Design Software Available

Lattice has released a new version of our downloadable ispLEVER Starter
software, concurrent with version 6.0. Device support includes the 90nm
LatticeECP2-50 and can be downloaded here:
http://www.latticesemi.com/products/...verstarter.cfm

Regards,
Bart Borosky, Lattice

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  #2 (permalink)  
Old 05-20-2006, 08:44 AM
Antti Lukats
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Default Re: ispLEVER Starter 6.0 FPGA Design Software Available

"bart" <[email protected]> schrieb im Newsbeitrag
news:[email protected] oups.com...
> Lattice has released a new version of our downloadable ispLEVER Starter
> software, concurrent with version 6.0. Device support includes the 90nm
> LatticeECP2-50 and can be downloaded here:
> http://www.latticesemi.com/products/...verstarter.cfm
>
> Regards,
> Bart Borosky, Lattice
>


are XP devices now suported in schematic?

antti


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  #3 (permalink)  
Old 05-20-2006, 09:33 AM
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Default Re: ispLEVER Starter 6.0 FPGA Design Software Available


bart wrote:
> Lattice has released a new version of our downloadable ispLEVER Starter
> software, concurrent with version 6.0. Device support includes the 90nm
> LatticeECP2-50 and can be downloaded here:
> http://www.latticesemi.com/products/...verstarter.cfm


Native Fedora/Debian linux versions?

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  #4 (permalink)  
Old 05-20-2006, 10:48 AM
Piotr Wyderski
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Default Re: ispLEVER Starter 6.0 FPGA Design Software Available

bart wrote:

> Lattice has released a new version of our downloadable
> ispLEVER Starter software


Still without even the simplest free simulator?

Best regards
Piotr Wyderski

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  #5 (permalink)  
Old 05-21-2006, 08:54 PM
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Default Re: ispLEVER Starter 6.0 FPGA Design Software Available

Hi Antti,
ispLever now supports schematic for FPGA's as well as CPLD's.

Luc
On Sat, 20 May 2006 09:44:40 +0200, "Antti Lukats"
<[email protected]> wrote:

>"bart" <[email protected]> schrieb im Newsbeitrag
>news:[email protected] roups.com...
>> Lattice has released a new version of our downloadable ispLEVER Starter
>> software, concurrent with version 6.0. Device support includes the 90nm
>> LatticeECP2-50 and can be downloaded here:
>> http://www.latticesemi.com/products/...verstarter.cfm
>>
>> Regards,
>> Bart Borosky, Lattice
>>

>
>are XP devices now suported in schematic?
>
>antti
>

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  #6 (permalink)  
Old 05-21-2006, 08:59 PM
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Default Re: ispLEVER Starter 6.0 FPGA Design Software Available

Piotr,
In my opinion, if your design needs a simulator, then you better spend
some money on a real good simulator. BTW, the full version of ispLEVER
has ModelSim as simulator and the list price on Lattice's website is
$695, and when you order online 'only' $495. For this price you get
the OEM version of ModelSim - and this is by far the best deal you can
get

Regards,
Luc

On Sat, 20 May 2006 11:48:47 +0200, "Piotr Wyderski"
<[email protected]> wrote:

>bart wrote:
>
>> Lattice has released a new version of our downloadable
>> ispLEVER Starter software

>
>Still without even the simplest free simulator?
>
> Best regards
> Piotr Wyderski

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  #7 (permalink)  
Old 05-22-2006, 03:48 PM
johnp
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Default Re: ispLEVER Starter 6.0 FPGA Design Software Available

Any idea what the limitations of the OEM version of Modelsim are for
the
Lattice OEM version?

John Providenza

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  #8 (permalink)  
Old 05-22-2006, 04:25 PM
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Default Re: ispLEVER Starter 6.0 FPGA Design Software Available

John,

No X-Tracer
25-30% slower as full version (Altera has same limitation, Xilinx has
even slower version)

That's it.

Luc

On 22 May 2006 07:48:01 -0700, "johnp" <[email protected]>
wrote:

>Any idea what the limitations of the OEM version of Modelsim are for
>the
>Lattice OEM version?
>
>John Providenza

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  #9 (permalink)  
Old 05-22-2006, 05:55 PM
Piotr Wyderski
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Default Re: ispLEVER Starter 6.0 FPGA Design Software Available

[email protected] wrote:

> In my opinion, if your design needs a simulator


Every design needs a simulator. Even as simple as that one from
Quartus Webpack -- it is still infinitely better than no simulator.

> For this price you get the OEM version of ModelSim - and this
> is by far the best deal you can get


Currently the best deal I can get is not to use Lattice or Actel
parts -- the other vendors provide all the necessary tools.

Best regards
Piotr Wyderski

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  #10 (permalink)  
Old 05-22-2006, 06:11 PM
Antti
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Default Re: ispLEVER Starter 6.0 FPGA Design Software Available

I use xilinx build in simulator for Lattice designs
or ok usually I am not doing that either.

but sure a simulator is a nice a have feature (when it is available)

Antti

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  #11 (permalink)  
Old 05-22-2006, 08:24 PM
johnp
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Default Re: ispLEVER Starter 6.0 FPGA Design Software Available

Luc -

The last version of ModelSim/Altera that I purchased had a limitation
of the number of instantiations you were allowed. If I started
manually
instantiating IO buffers for wide ram busses, I'd hit the limit and
ModelSim
would refuse to run.

John Providenza

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  #12 (permalink)  
Old 05-22-2006, 10:07 PM
Ben Twijnstra
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Default Re: ispLEVER Starter 6.0 FPGA Design Software Available

John,

> Luc -
>
> The last version of ModelSim/Altera that I purchased had a limitation
> of the number of instantiations you were allowed. If I started
> manually instantiating IO buffers for wide ram busses, I'd hit the
> limit and ModelSim would refuse to run.


There is indeed a 255-instance limit, so that is correct. However, as you
can see from being able to run gate-level simulations, this limitation is
not there when actually instantiating Altera cell primitives.

Thus, I'm not entirely sure how you ran into this limit, unless you wrapped
the BIDIRs into something slightly higher-level.

BTW: Why did you instantiate those IO buffers? So far I've always been able
to infer them.

Best regards,


Ben

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  #13 (permalink)  
Old 05-26-2006, 02:39 AM
Ron
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Default Re: ispLEVER Starter 6.0 FPGA Design Software Available

Piotr Wyderski wrote:
> Still without even the simplest free simulator?


I use the free Icarus Simulator at:
http://www.icarus.com/eda/verilog/
and I think it's great. Although it doesn't have a GUI interface, it's
very simple and easy to use. I even use it in preference to the free
simulators offered by some of the FPGA vendors, and have used it to
develop a 2,000+ line Verilog program to implement the Elliptic Curve
Factoring method an FPGA.

Ron

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