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Old 10-25-2007, 04:37 PM
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Default ISE PACE Question

HI, I have a Xilinx ISE - PACE editor question-

I am using the schematic editor for now just to get familar with the
tools and the fact I don't understand a HDL yet.

What Iam trying to do is very basic and I am just missing a step or
setting somewhere most likely ...

To reproduce the issue - using ISE 9.2i (or 8.2i)

1) Start ISE project navigator
2) Create a new project called TESTPACE
3) TopLevel source is schematic
4) Family XC95000 CPLD, XC95108, PC84, -7, XST (VHDL/Verilog),
MOdelsim XE Verilog, verilog
5) New Source, Schematic, name - top
6) Finish, next, finish
7) Add logic symbol - decoder d2_4e
8) Add7 i/o markers - Leave default names
9) Save top.sch
10) Run Assign package pins
11) UCF file is created message
12) Rreview I/O pins - all are visible and can be placed - close file
- don't save
13) Add second symbol - flip flop - fd
14) remove the i/o marker from D0 on the decoder and run a wire from
D0 to C
15) Add I/o markers to D and Q
16) Save top.sch
17) Run Assign package pins
18) only D C and Q are available to be placed (Note why is C available
to be placed on a pin when it is now only used internally.

Suggestions welcome.

Thanks

Glenn

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Old 10-25-2007, 06:28 PM
Gabor
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Default Re: ISE PACE Question

On Oct 25, 11:37 am, [email protected] wrote:
> HI, I have a Xilinx ISE - PACE editor question-
>
> I am using the schematic editor for now just to get familar with the
> tools and the fact I don't understand a HDL yet.
>
> What Iam trying to do is very basic and I am just missing a step or
> setting somewhere most likely ...
>
> To reproduce the issue - using ISE 9.2i (or 8.2i)
>
> 1) Start ISE project navigator
> 2) Create a new project called TESTPACE
> 3) TopLevel source is schematic
> 4) Family XC95000 CPLD, XC95108, PC84, -7, XST (VHDL/Verilog),
> MOdelsim XE Verilog, verilog
> 5) New Source, Schematic, name - top
> 6) Finish, next, finish
> 7) Add logic symbol - decoder d2_4e
> 8) Add7 i/o markers - Leave default names
> 9) Save top.sch
> 10) Run Assign package pins
> 11) UCF file is created message
> 12) Rreview I/O pins - all are visible and can be placed - close file
> - don't save
> 13) Add second symbol - flip flop - fd
> 14) remove the i/o marker from D0 on the decoder and run a wire from
> D0 to C
> 15) Add I/o markers to D and Q
> 16) Save top.sch
> 17) Run Assign package pins
> 18) only D C and Q are available to be placed (Note why is C available
> to be placed on a pin when it is now only used internally.
>
> Suggestions welcome.
>
> Thanks
>
> Glenn



One of the known bugs of recent ISE releases requires you to clean up
the project (remove old object files). I don't use the schematic
flow, but this sounds like one of those issues, i.e. remainders of
the first build showing up when you run PACE.

HTH,
Gabor

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