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Old 04-24-2006, 04:58 PM
Eli Hughes
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Default ISE 8.1 Sub module Synthesis

Hello:

I ran into an issue (which may be a 'feature') in version 8.1 of ISE.
When I have a simple verilog project with a top level module, I can no
longer right click on one of the sub verilog modules for synthesis. In
previous versions (7.1, etc) I could right click on any of the sub
modules and syntehsize them indivdually. In 8.1 the only processes I
have for a submodule are to check syntax, generate schematic symbol and
view instantiation template.


This is a real annoyance as it is nice to add submodules to my project
to synthesize/simulate them indivually before integrating them into my
top level module. If there a way to turn this 'feature' off?

-Eli
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  #2 (permalink)  
Old 04-24-2006, 05:29 PM
Zara
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Default Re: ISE 8.1 Sub module Synthesis

On Mon, 24 Apr 2006 10:58:46 -0400, Eli Hughes <[email protected]> wrote:

>Hello:
>
>I ran into an issue (which may be a 'feature') in version 8.1 of ISE.
>When I have a simple verilog project with a top level module, I can no
>longer right click on one of the sub verilog modules for synthesis. In
>previous versions (7.1, etc) I could right click on any of the sub
>modules and syntehsize them indivdually. In 8.1 the only processes I
>have for a submodule are to check syntax, generate schematic symbol and
>view instantiation template.
>
>
>This is a real annoyance as it is nice to add submodules to my project
>to synthesize/simulate them indivually before integrating them into my
>top level module. If there a way to turn this 'feature' off?
>
>-Eli



I don't know if it will work in verilgo, but I soppes it will. It
works on VHDL. Right click on source node , "Select as Top Module". Do
remember to reselect original Top module when done.

I should classify it a s a real feature, because you can bypass it
when needed, but you save time when double clicking on Synthesis with
the wrong node selected.

Best regards,

Zara
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  #3 (permalink)  
Old 04-25-2006, 03:39 AM
Gerhard Hoffmann
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Default Re: ISE 8.1 Sub module Synthesis

On Mon, 24 Apr 2006 17:29:34 +0200, Zara <[email protected]> wrote:


>I don't know if it will work in verilgo, but I soppes it will. It
>works on VHDL. Right click on source node , "Select as Top Module". Do
>remember to reselect original Top module when done.


I did this, too (vhdl), but then the "real top module" user constraint file was
changed to empty. Gave not so funny results with the router deciding arbitrarily
which pin is wich. I had connected new hardware to the eval board and
assumed that I had killed the Virtex4 :-(
Luckily, it was too late already to order a new one.
It would help if one could see in the log files what the reason was for a
signal to end up at a certain pin.

Dependency checking seems to be messed up in 8.1 . That could be a
reason for the above, too.
Today, I got warnings about incompatible components and instantiatons.
I removed some instantiations completely ( commenting out large
blocks is _such_ a fun in VHDL..) but still they appeared in the error list.
It looks like ISE has made own copies of my source files.
I don't use the internal editor but gvim, so maybe ISE does not see every
file update?
Using Project -> CleanupProjectFiles reduced the number of error messages
by 80%, but not completely.

And, because I'm in the mood: The ISE gui is almost dead after kicking
off a synthesis. Sometimes, the routing has run to completion before
the gui wakes up again. The first run after booting seems not to be
affected by this. I use the windows task manager to keep track of
what's going on (shows top CPU eating processes).

When I double click on "ConfigureDevice" to kick off synthesis & everything,
and do 5 times edit-compile-load-measure, then I end up with 5 incarnations of
IMPACT, as if one wasn't enough, and each one asking me what to do and
if it should update the project file on exit, as if anything had changed.

ISE knows enough about my project so that one doubleclick should be enough
to go from source to logic analyzer. We had that already in XC3020 times.
Impact should not ask ME if it needs a mask file for verify.

I changed from 7.1 to 8.1 because 7.1 crashed may computer abt. 6 times
a day. Those crashes are history with 8.1, but all in all, things have
gone from bad to worse.
Retreating to 6.3 like others here do is probably no option for a virtex4.
Perhaps I should convert everything to makefiles.

regards, Gerhard

environment: Athlon64-4000+, 2 GB RAM, striped raptors :-), XP,
Modelsim PE, ISE 8.1.3, ML402, platform cable USB, vim
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  #4 (permalink)  
Old 04-25-2006, 07:29 AM
Zara
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Default Re: ISE 8.1 Sub module Synthesis

On Tue, 25 Apr 2006 03:39:22 +0200, Gerhard Hoffmann
<[email protected]> wrote:

>On Mon, 24 Apr 2006 17:29:34 +0200, Zara <[email protected]> wrote:
>
>
>>I don't know if it will work in verilgo, but I soppes it will. It
>>works on VHDL. Right click on source node , "Select as Top Module". Do
>>remember to reselect original Top module when done.

>
>I did this, too (vhdl), but then the "real top module" user constraint file was
>changed to empty. Gave not so funny results with the router deciding arbitrarily
>which pin is wich. I had connected new hardware to the eval board and
>assumed that I had killed the Virtex4 :-(
>Luckily, it was too late already to order a new one.
>It would help if one could see in the log files what the reason was for a
>signal to end up at a certain pin.


Well, never tried it like that. I just limit all work to synthesis
when my tuop module is not *the top module*.

>
>Dependency checking seems to be messed up in 8.1 . That could be a
>reason for the above, too.
>Today, I got warnings about incompatible components and instantiatons.
>I removed some instantiations completely ( commenting out large
>blocks is _such_ a fun in VHDL..) but still they appeared in the error list.
>It looks like ISE has made own copies of my source files.
>I don't use the internal editor but gvim, so maybe ISE does not see every
>file update?


I use Crimson Editor, ans everything works fine.

>Using Project -> CleanupProjectFiles reduced the number of error messages
>by 80%, but not completely.
>
>And, because I'm in the mood: The ISE gui is almost dead after kicking
>off a synthesis. Sometimes, the routing has run to completion before
>the gui wakes up again. The first run after booting seems not to be
>affected by this. I use the windows task manager to keep track of
>what's going on (shows top CPU eating processes).


It is the "feature" of reading all reports to create the desgin
summary. It is nice, but it is a heavy load.

BTW, I run ISE on an athlon dual core machine, and it is funny to see
50% of the "CPU" (that is, a full core) used up by
synthesis/xlate/map/par while the other 50%( the other full core) is
used byISE itself to keep reports updated. Most ilustrating.

>
>When I double click on "ConfigureDevice" to kick off synthesis & everything,
>and do 5 times edit-compile-load-measure, then I end up with 5 incarnations of
>IMPACT, as if one wasn't enough, and each one asking me what to do and
>if it should update the project file on exit, as if anything had changed.


Yes, that is really stupid.

>
>ISE knows enough about my project so that one doubleclick should be enough
>to go from source to logic analyzer. We had that already in XC3020 times.
>Impact should not ask ME if it needs a mask file for verify.


Right.

>
>I changed from 7.1 to 8.1 because 7.1 crashed may computer abt. 6 times
>a day. Those crashes are history with 8.1, but all in all, things have
>gone from bad to worse.
>Retreating to 6.3 like others here do is probably no option for a virtex4.
>Perhaps I should convert everything to makefiles.


Best luck. I use only Spartan3, and I can keep up with some of these
nuisances. Going back is not a choice.

Best regards.

Zara
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