FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal


Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 04-10-2006, 08:53 PM
Ira Thorpe
Posts: n/a
Default Interfacing to DDS v5.0 in System Generator

I have a system generator model that utilizes the DDS v4.1 block. I
wish to upgrade to the DDS v5.0 block to take advantage of some of the
new features. However I have noticed that the interface has changed.
My specific application utilizes the phase increment register and a
constant phase offset of zero. In my v4.0 design, the accumulator width
is set to 32 bits which configures the data input as a 32.32 unsigned
integer. The output width is also configurable I use a 16-bit width,
which gives a 16.15 signed output and a signal ranging between +/- 1
When I try using the v5.0 core with the Frequency set to
programmable, it asks for a signed input at the data port. That seems
odd because the value should always be positive. The width of this
input seems to be set by the frequency resolution. Also I see nowhere
where I can set the output resolution or amplitude and the signal is
now between +/- 0.5 rather than +/- 1. How can I configure the new
core to have the same interfaces as the old ones.? Thanks,
-Ira Thorpe

Reply With Quote


Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On

Similar Threads
Thread Thread Starter Forum Replies Last Post
DSP Builder @ System Generator [email protected] FPGA 1 03-15-2006 10:28 AM
How to use a .coe file for rom/ram in system generator Glenn FPGA 0 02-23-2006 06:23 PM
System Generator Chintan Trehan FPGA 0 06-20-2005 11:12 PM
System Generator. Nirav Shah FPGA 2 10-01-2004 08:44 PM
System Generator and Microblaze Matt FPGA 0 01-12-2004 11:23 PM

All times are GMT +1. The time now is 06:09 PM.

Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved