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  #1 (permalink)  
Old 04-05-2006, 07:58 PM
Jeff Brower
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Default initializing arrays with Verilog and XST

All-

If I have an array of registers like:

reg [3:0] reg_array [3:0];

how to initialize elements with different values?

I tried various combinations such as:

// synthesis attribute INIT of reg_array[0] is 4'h1;
// synthesis attribute INIT of reg_array[1] is 4'h9;

but XST continues to say something like:

Cannot find <reg_array[0]> in module <test_mod>, property <INIT> with
Value <4'h1> is ignored.

I have been searching Xilinx site and group posts for array
initialization examples but no luck yet.

Thank you.

-Jeff

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  #2 (permalink)  
Old 04-05-2006, 08:35 PM
John_H
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Default Re: initializing arrays with Verilog and XST

XST may support the initial block:
initial
begin
reg_array[0] = 4'h1;
reg_array[1] = 4'h9;
....
end

They *do* support initial assignment to simple registers:
reg [3:0] RegArrA = 4'h1;
reg [3:0] RegArrB = 4'h9;


"Jeff Brower" <[email protected]> wrote in message
news:[email protected] ups.com...
> All-
>
> If I have an array of registers like:
>
> reg [3:0] reg_array [3:0];
>
> how to initialize elements with different values?
>
> I tried various combinations such as:
>
> // synthesis attribute INIT of reg_array[0] is 4'h1;
> // synthesis attribute INIT of reg_array[1] is 4'h9;
>
> but XST continues to say something like:
>
> Cannot find <reg_array[0]> in module <test_mod>, property <INIT> with
> Value <4'h1> is ignored.
>
> I have been searching Xilinx site and group posts for array
> initialization examples but no luck yet.
>
> Thank you.
>
> -Jeff
>



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  #3 (permalink)  
Old 04-06-2006, 01:03 AM
Jeff Brower
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Default Re: initializing arrays with Verilog and XST

John-

> XST may support the initial block:
> initial
> begin
> reg_array[0] = 4'h1;
> reg_array[1] = 4'h9;
> ...
> end
>
> They *do* support initial assignment to simple registers:
> reg [3:0] RegArrA = 4'h1;
> reg [3:0] RegArrB = 4'h9;


Thanks for the reply.

Yes single reg initialization works Ok. But I've not figured out yet
how to init one or more that are part of an array declaration.

I recall that in the past XST has referred to a register bit as
something like reg_array_0, and that could be used in the INIT
attribute, but I don't know XST's method for specifying an array
element, or a bit within an array element.

-Jeff

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  #4 (permalink)  
Old 04-06-2006, 03:26 AM
vssumesh
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Default Re: initializing arrays with Verilog and XST

This may not be the correct method to do it; but why dont you look at
the synthesized output (synthesizing is done with out including the
INIT part) and find out the name of the registeres you want to
initialise. And then use INIT in the code with that name. Try to use
INIT in the ucf. Also you can use microsoft excel to generate INIT
strings if the array is large.
regards
Sumesh V S

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  #5 (permalink)  
Old 04-06-2006, 06:18 AM
Jeff Brower
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Default Re: initializing arrays with Verilog and XST

Sumesh-

> This may not be the correct method to do it; but why dont you look at
> the synthesized output (synthesizing is done with out including the
> INIT part) and find out the name of the registeres you want to
> initialise. And then use INIT in the code with that name. Try to use
> INIT in the ucf. Also you can use microsoft excel to generate INIT
> strings if the array is large.


Thanks very much Sumesh, that was a good idea. I located the registers
in the RTL schematic, and I found that I can do:

reg [3:0] reg_array [3:0];

// synthesis attribute INIT of reg_array is 8'h17

which I'm hoping will initialize the first 2 registers in the array.
But this:

// synthesis attribute INIT of reg_array_0_0 is 1'b1

still gets the XST "ignored" message (I was hoping it might initialize
the first bit in the first register).

Questions for anyone:

1) Does XST allocate an array of registers starting with
least-significant index?

2) Is there some Xilinx documentation on this that I'm just not
finding? App notes? Something else?

-Jeff

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