FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 04-28-2006, 05:18 AM
Jeff Brower
Guest
 
Posts: n/a
Default initializing array of registers in XST

Steve, Peter and Austin-

Can you give definitive instructions -- or point me to who can -- for
initializing an array of registers?

I need to initialize an array of registers in one way, set values
differently upon Reset, and set values differently again during normal
operation. I have this code:

reg [31:0] array [11:0];

// synthesis attribute INIT of array is 64'h0C0001820C000080;

which is intended to initialize the first 2 elements of the array, but
doesn't set any bits although XST appears to "accept" the INIT
attribute. What is needed? The whole 384 bits set with one number?
Can this be done using 384'hxxxx... syntax?

I have opened a webcase through our local FAE, but after about 3 weeks
have no clear answers other than to instantiate a RAM using CoreGen and
use a .coe file, or read in a .dat file for simulation purposes but not
synthesis. To use a RAM I would have to switch the array row/column to
get XST to recognize asynchronous reads, and I have done that in other
cases, but in this case I can't because I actually need 32-bit
registers (they are accessible via a host processor).

For something like array initialization, there has to be a solid answer
-- hopefully some actual code showing how to do it.

Thanks.

-Jeff

Reply With Quote
  #2 (permalink)  
Old 04-28-2006, 07:55 PM
Dave Pollum
Guest
 
Posts: n/a
Default Re: initializing array of registers in XST


Jeff Brower wrote:
> Steve, Peter and Austin-
>
> Can you give definitive instructions -- or point me to who can -- for
> initializing an array of registers?
>
> I need to initialize an array of registers in one way, set values
> differently upon Reset, and set values differently again during normal
> operation. I have this code:
>
> reg [31:0] array [11:0];
>
> // synthesis attribute INIT of array is 64'h0C0001820C000080;
>
> which is intended to initialize the first 2 elements of the array, but
> doesn't set any bits although XST appears to "accept" the INIT
> attribute. What is needed? The whole 384 bits set with one number?
> Can this be done using 384'hxxxx... syntax?
>
> I have opened a webcase through our local FAE, but after about 3 weeks
> have no clear answers other than to instantiate a RAM using CoreGen and
> use a .coe file, or read in a .dat file for simulation purposes but not
> synthesis. To use a RAM I would have to switch the array row/column to
> get XST to recognize asynchronous reads, and I have done that in other
> cases, but in this case I can't because I actually need 32-bit
> registers (they are accessible via a host processor).
>
> For something like array initialization, there has to be a solid answer
> -- hopefully some actual code showing how to do it.
>
> Thanks.
>
> -Jeff


Jeff;
I don't have an answer for you, but since your code appears to be in
verilog, I wonder if you'd get a response by posting in
comp.lang.verilog.
-Dave P

Reply With Quote
  #3 (permalink)  
Old 04-28-2006, 09:51 PM
Brian Dam Pedersen
Guest
 
Posts: n/a
Default Re: initializing array of registers in XST

ISE 8 supports initialization of registers in an initial block, so

initial begin
array[0]=1234;
array[1]=5678;
Reply With Quote
  #4 (permalink)  
Old 04-28-2006, 09:57 PM
Jeff Brower
Guest
 
Posts: n/a
Default Re: initializing array of registers in XST

Brian-

Thanks Brian for your reply.

> initial begin
> array[0]=1234;
> array[1]=5678;
> .
> .
> array[11]=0101;
> end


For simulation only? Or will this work for synthesis.

-Jeff

Reply With Quote
  #5 (permalink)  
Old 04-28-2006, 10:02 PM
Jeff Brower
Guest
 
Posts: n/a
Default Re: initializing array of registers in XST

Dave-

> I don't have an answer for you, but since your code appears to be in
> verilog, I wonder if you'd get a response by posting in
> comp.lang.verilog


Thanks very much for your reply. Yes posting on the Verilog group
might bring some ideas so I will do that.

But at the base, this is an XST issue. I can use UCF file, synthesis
attribute -- whatever works. I just need to know what works in XST,
for Xilinx FPGA devices, and be done with it.

-Jeff

Reply With Quote
  #6 (permalink)  
Old 04-28-2006, 10:28 PM
Andy
Guest
 
Posts: n/a
Default Re: initializing array of registers in XST

IIRC, xilinx initial values (after config) and built-in set/reset
values must be the same (in fact, I know synplicity will take the reset
value for the initial value). If you really need "reset" values
different from initial ones, then you'll have to code a synchronous
reset in with your logic. You'd have to be careful that it does not
confuse your "logic" reset with a built-in reset function. Maybe if
you coded a reset for the initial value (then hardwired it to optimize
it out), and subsequent to that, a secondary "reset" function, that
might work:

This is in vhdl, but here's what I'd try:

init <= '0' -- hardwired off
process (clk) -- no async reset!
begin
if rising_edge(clk) then
if init = '1' then -- hopefully synth will take this as the "reset"
a <= initial_value;
elsif reset = '1' then -- this will just be part of operational logic
a <= reset_value;
else
a <= operational_value;
end if
end if;
end process;

You're out of luck if you need different initial and async reset
values.

Hope this helps,

Andy

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Initializing Array from String Uwe Bonnes Verilog 5 03-03-2007 03:54 PM
Using contents of one array to index into another array kb33 Verilog 3 10-08-2006 07:12 PM
initializing array of registers [email protected] Verilog 1 05-06-2006 11:22 PM
Initializing array of BlockRAM instances in verilog [email protected] FPGA 5 04-25-2006 08:30 PM
Initializing array of BlockRAM instances in verilog [email protected] Verilog 1 04-22-2006 08:09 AM


All times are GMT +1. The time now is 07:19 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved