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Old 05-26-2006, 07:41 PM
Jeff Brower
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Default initial block processing in XST 8.1, part 2

All-

On pg 498 of the 8.1i XST Users Guide, it says "Since initial blocks
are ignored during synthesis...".

But our FAE has sent Verilog examples showing initial block examples
for RAMs, FSMs, and FFs, saying it's not just for simulation, but also
used during synthesis.

Can I ask Xilinx persons to confirm that XST 8.1 is doing this
synthesis inside initial blocks, and this behavior isn't going to go
away, even though it's not Verilog 2001 complaint?

Steve (Knapp), can you help?

Thanks.

-Jeff

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