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  #1 (permalink)  
Old 03-16-2007, 03:35 PM
Guest
 
Posts: n/a
Default init of FPGA's Block-RAMs.

Bonjour,

My name is Julien Lochen, I work as FPGA Design Engineer in France.

My question is about the init of FPGA's RAMs.

In my design, some data are stored in a block-RAM.

I need to init each byte stored in the block-RAM, but THE INIT VALUE
ARE NOT THE SAME.

To do this, I use the constraint file, in which I use the following
keyword :

"INIT_00 = 256'h ...
INIT_01 = 256'h ...
...
INIT_3F = 256'h ..."

The block-RAM is mapped as follow : 256 lines of 1 byte.

The question is :

If I want to init only the five first addresses to "1", and the rest
of the block-RAM to zero, am I correct if I write :
"INIT_00 =
256'h000000000000000000000000000000000000000000000 0000000FFFFFFFFFFFF;
INIT_01 =
256'h000000000000000000000000000000000000000000000 0000000000000000000;
...
INIT_3F =
256'h000000000000000000000000000000000000000000000 0000000000000000000;"

regards, Julien

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  #2 (permalink)  
Old 03-16-2007, 05:01 PM
Barry Brown
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Posts: n/a
Default Re: init of FPGA's Block-RAMs.

Hi Julien,

For synthesis with Synplify, I initialize memories as shown below . The
text files contain the memory contents, one memory location per line.

Barry Brown


// for Synplify ram inference
reg [9:0] RdAddr_reg;
reg [17:0] mem1 [0:1023]/* synthesis syn_ramstyle="no_rw_check" */;
reg [17:0] mem2 [0:1023]/* synthesis syn_ramstyle="no_rw_check" */;

initial begin // ROM values stored in these files
$readmemh("Stage1_Ram1.txt", mem1);
$readmemh("Stage1_Ram2.txt", mem2);
end


// >>>>>>>>>>>>>>>> HARDWARE DESCRIPTION BEGINS HERE >>>>>>>>>>>>>>>>>

// >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>>
// This code causes Synplify to infer dual port block RAMs.
// >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> >>>>>>>>>>>>>>>>>>>>>
always @(posedge WrClk)
begin : DP_BRAM
if (WrEn[1])
mem1[WrAddr] <= WrData;
if (WrEn[2])
mem2[WrAddr] <= WrData;
end // DP_BRAM

always @(posedge RdClk)
begin : BRAM_reg
RdAddr_reg <= RdAddr;
end // BRAM_reg

assign RdData1 = mem1[RdAddr_reg];
assign RdData2 = mem2[RdAddr_reg];


Stage1_Ram1.txt :
00002
00007
00010
0001C
0002C
00040
00057
00072
00090
000B2
000D8
00101
0012E
0015F
00193
etc.




<[email protected]> wrote in message
news:[email protected] oups.com...
> Bonjour,
>
> My name is Julien Lochen, I work as FPGA Design Engineer in France.
>
> My question is about the init of FPGA's RAMs.
>
> In my design, some data are stored in a block-RAM.
>
> I need to init each byte stored in the block-RAM, but THE INIT VALUE
> ARE NOT THE SAME.
>
> To do this, I use the constraint file, in which I use the following
> keyword :
>
> "INIT_00 = 256'h ...
> INIT_01 = 256'h ...
> ...
> INIT_3F = 256'h ..."
>
> The block-RAM is mapped as follow : 256 lines of 1 byte.
>
> The question is :
>
> If I want to init only the five first addresses to "1", and the rest
> of the block-RAM to zero, am I correct if I write :
> "INIT_00 =
> 256'h000000000000000000000000000000000000000000000 0000000FFFFFFFFFFFF;
> INIT_01 =
> 256'h000000000000000000000000000000000000000000000 0000000000000000000;
> ...
> INIT_3F =
> 256'h000000000000000000000000000000000000000000000 0000000000000000000;"
>
> regards, Julien
>



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  #3 (permalink)  
Old 03-16-2007, 05:21 PM
John_H
Guest
 
Posts: n/a
Default Re: init of FPGA's Block-RAMs.

It looks like you have what you need if you ignore the fact that there are
12 F digits in your string rather than five 1s or five FFs.

The question is where do you want to apply the INITs? The INITs work fine
in the .ucf file. If you want them in your source code, you have to
instantiate the BlockRAM primitive. Is that what you've done? In Verilog,
I prefer to use the inline parameters rather than synthesis attributes or
defparam values. One of these three methods will need to be used to attach
the INITs properly to the instantiated BlockRAM. Which do you prefer?

If you're inferring your memory, look to your synthesizer's reference for
initialization. An initial block will work for some synthesizers and Barry
Brown pointed out how Synplify likes to handle file-based memory
initialization for Verilog.

- John_H


<[email protected]> wrote in message
news:[email protected] oups.com...
> Bonjour,
>
> My name is Julien Lochen, I work as FPGA Design Engineer in France.
>
> My question is about the init of FPGA's RAMs.
>
> In my design, some data are stored in a block-RAM.
>
> I need to init each byte stored in the block-RAM, but THE INIT VALUE
> ARE NOT THE SAME.
>
> To do this, I use the constraint file, in which I use the following
> keyword :
>
> "INIT_00 = 256'h ...
> INIT_01 = 256'h ...
> ...
> INIT_3F = 256'h ..."
>
> The block-RAM is mapped as follow : 256 lines of 1 byte.
>
> The question is :
>
> If I want to init only the five first addresses to "1", and the rest
> of the block-RAM to zero, am I correct if I write :
> "INIT_00 =
> 256'h000000000000000000000000000000000000000000000 0000000FFFFFFFFFFFF;
> INIT_01 =
> 256'h000000000000000000000000000000000000000000000 0000000000000000000;
> ...
> INIT_3F =
> 256'h000000000000000000000000000000000000000000000 0000000000000000000;"
>
> regards, Julien
>



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  #4 (permalink)  
Old 03-18-2007, 05:56 PM
Jim Wu
Guest
 
Posts: n/a
Default Re: init of FPGA's Block-RAMs.

On Mar 16, 9:35 am, [email protected] wrote:
> Bonjour,
>
> My name is Julien Lochen, I work as FPGA Design Engineer in France.
>
> My question is about the init of FPGA's RAMs.
>
> In my design, some data are stored in a block-RAM.
>
> I need to init each byte stored in the block-RAM, but THE INIT VALUE
> ARE NOT THE SAME.
>
> To do this, I use the constraint file, in which I use the following
> keyword :
>
> "INIT_00 = 256'h ...
> INIT_01 = 256'h ...
> ...
> INIT_3F = 256'h ..."
>
> The block-RAM is mapped as follow : 256 lines of 1 byte.
>
> The question is :
>
> If I want to init only the five first addresses to "1", and the rest
> of the block-RAM to zero, am I correct if I write :
> "INIT_00 =
> 256'h000000000000000000000000000000000000000000000 0000000FFFFFFFFFFFF;
> INIT_01 =
> 256'h000000000000000000000000000000000000000000000 0000000000000000000;
> ...
> INIT_3F =
> 256'h000000000000000000000000000000000000000000000 0000000000000000000;"
>
> regards, Julien


The "first five addresses" are different for different BRAM data width
setting, so it is hard to say whether your values in UCF is correct or
not without knowing the bus width.

Cheers,
Jim
http://home.comcast.net/~jimwu88/tools/

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