FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 03-22-2005, 08:08 PM
Nemesis
Guest
 
Posts: n/a
Default Importing waveforms from ASCII files

Hi all,
I'm trying to test a filter I implemented with Xilinx ISE 6.1, so I
created a testbench waveform. I'd like to import the input waveform from
an ASCII file because the Pattern Generator can create only simple
patterns.

--
And on the 8th Day God said, "Murphy, take over!"

|\ | |HomePage : http://nem01.altervista.org
| \|emesis |XPN (my nr): http://xpn.altervista.org

Reply With Quote
  #2 (permalink)  
Old 04-13-2005, 06:39 PM
Engineering Guy
Guest
 
Posts: n/a
Default Re: Importing waveforms from ASCII files

Nemesis wrote:

> Hi all,
> I'm trying to test a filter I implemented with Xilinx ISE 6.1, so I
> created a testbench waveform. I'd like to import the input waveform from
> an ASCII file because the Pattern Generator can create only simple
> patterns.
>

Try something like this:

-- Copyright (c) 2003-2005 by Aldec, Inc. All rights reserved.
--
------------------------------------------------------------------------------------
--
-- Created on Wednesday 2005-04-13, 19:37:24
--
------------------------------------------------------------------------------------
-- Details:
-- Type: Clocked file stimulus
-- Data width: 16
-- Radix of values stored in the file is binary
-- Clock input CLK sensitive to rising edge
-- Clock enable input CE active high
-- Output Q
------------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {file_stim_clkd} architecture {file_stim_arch}}

library IEEE;
use IEEE.std_logic_1164.all;

entity file_stim_clkd is
port(
CLK : in std_logic;
CE : in std_logic;
Q : out std_logic_vector(15 downto 0)
);
end entity;

--}} End of automatically maintained section

library IEEE;
use STD.textio.all;
use IEEE.std_logic_textio.all;

architecture file_stim_arch of file_stim_clkd is
constant file_name : string(1 to 12) := "stimulus.txt";
file stimulus : text open READ_MODE is file_name;
begin
reader : process
variable line_read : line;
variable signal_val : std_logic_vector(15 downto 0);
begin
processing : while not endfile(stimulus) loop

readline(stimulus, line_read);
read(line_read, signal_val);

wait until (CE='1' and rising_edge(CLK));

Q <= signal_val;

end loop processing;

report "Reached the end of the file:" & file_name & '.'
severity NOTE;

file_close(stimulus);
wait;

end process reader;

end architecture;
Reply With Quote
  #3 (permalink)  
Old 04-15-2005, 06:40 PM
Nemesis
Guest
 
Posts: n/a
Default Re: Importing waveforms from ASCII files

Mentre io pensavo ad una intro simpatica "Engineering Guy" scriveva:

>> Hi all,
>> I'm trying to test a filter I implemented with Xilinx ISE 6.1, so I
>> created a testbench waveform. I'd like to import the input waveform from
>> an ASCII file because the Pattern Generator can create only simple
>> patterns.
>>

> Try something like this:

[cut]

Thanks, finally I found a solution very close to yours.


--
Five out of four people have trouble with fractions.

|\ | |HomePage : http://nem01.altervista.org
| \|emesis |XPN (my nr): http://xpn.altervista.org

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
ASCII conversion raghu Verilog 4 10-06-2006 10:57 PM
editing waveforms under Linux steve FPGA 2 03-14-2005 09:29 PM
Help with importing a comp. as a netlist, edk6.2i Amir FPGA 1 12-21-2004 02:29 PM
importing a design from maxplus2 to quartus II ver 3 charles FPGA 1 06-16-2004 04:56 AM


All times are GMT +1. The time now is 11:01 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved