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  #1 (permalink)  
Old 05-18-2009, 09:26 PM
VIPS
Guest
 
Posts: n/a
Default i2c Start and stop detection

Hi all

I am implementing the I2C Slave and I am using the I2C clock SCL for
detecting the start and stop condition . I am detecting the start and
stop successfully in simulation but i am not able to do the same in
the post synthesis scenario. More so I am getting a setup time
violation for the same in the timing analysis . I am running the I2C
at a very slow speed of 100KHz.

The code is below

process (SDA_IN, START_RST,rst)
begin
if rst ='1' then
STARTOP <='0';
-- elsif (START_RST = '1') then
-- STARTOP <= '0';
elsif (SDA_IN'event and SDA_IN = '0') then
STARTOP <= scl;
end if;
end process;
------------------------------------------------------------------------------
-- stop condition detection
process (RST, SCL, SDA_IN, STARTOP)
begin
if RST = '1' or SCL = '0' or STARTOP='1' then
STOPOP <= '0';
elsif SDA_IN = '1' and SDA_IN'event then
if SCL = '1' then
STOPOP <= '1';
end if ;

end if;
end process;

Can any one give me a reliable way to detect the start and stop
condition that the synthesis tool doesnot give any setup time
violation. I am not using a high clock for sampling as the requirement
is to use the SCL only. May be to save board resourse and space.

Help will be appreciated. I am using Altera max II CPLD and the
synthesis tool is quartus 9.0

Thanks

Vipul
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  #2 (permalink)  
Old 05-19-2009, 05:34 AM
pini_1234
Guest
 
Posts: n/a
Default

You might want to take a look on a work I did once on I2c.

I2C master connected and tested with LEON Processor
This design uses the open core's I2C master. The core's CPU interface is modified from WISHBONE to AMBA/APB. The latter is done in order to test the core and its new APB interface with LEON processor. LEON is written in VHDL therefor the core's VHDL RTL design is tested.
....



VHDL, verilog, design, verification, scripts, ...
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  #3 (permalink)  
Old 05-19-2009, 07:39 PM
Brad Smallridge
Guest
 
Posts: n/a
Default Re: i2c Start and stop detection

Dear Vipul,

Seems like you are always going to get
some sort of timing issue since the rst
signal and the SDA_IN signal are async.

Propagating the STARTOP signal forward
to the STOPOP reset circuitry also seems
like a bad idea for some reason I can't
quite articulate, except for an idea that
the start and stop signals should be
symetrical.

If you have a system clock, I would suggest
that you use registers at your SDA and SCL
inputs right at the IOs. Then use old values
of SDA and SCL to calculate your START and
STOP signals:

start_stop_procrocess(clk)
begin
if(clk'event and clk='1')then
STARTOP<='0';
STOPOP<='0';
SDA_1<=SDA_IN;
SDA_2<=SDA_1;
SCL_1<=SCL_IN;
if( SDA_1='0' and SDA_2='1' and SCL_1='1')then
STARTOP<='1';
end if;
if( SDA_1='1' and SDA_2='0' and SCL_1='1')then
STOPOP<='1';
end if;
end if;
end process;

This should be very clean as long as your system clock
and timing is OK. And it give clean oneshot reset signals
for your address and data registers.

Now if you are trying to run this from the SCL clock, perhaps
just taking the rst out of your process may work, or putting
it in the synchonous part of the block may work, and clean
up the code so that the both signals look symetrical:

start_procrocess(SDA_IN)
begin
if(SDA_IN'event and SDA_IN='0')then
if(rst='1')then
STARTOP<='0';
elsif(scl='1')then
STARTOP<='1';
else
STARTOP<='0';
end if;
end if;
end process;

stop_procrocess(SDA_IN)
begin
if(SDA_IN'event and SDA_IN='1')then
if(rst='1')then
STOPOP<='0';
elsif(scl='1')then
STOPOP<='1';
else
STOPOP<='0';
end if;
end if;
end process;

Then these signals need to be synched with scl clock
signal before you start messing with your data registers.
And you have to look for their edges since the SDA signal
can drop and not come up if it's sending a zero datum.

Using a system clock is a lot easier.

I haven't ever done a I2C slave so you might get better
answers elsewhere. Good luck.


Brad Smallridge
AiVision


"VIPS" <[email protected]> wrote in message
news:[email protected]m...
> Hi all
>
> I am implementing the I2C Slave and I am using the I2C clock SCL for
> detecting the start and stop condition . I am detecting the start and
> stop successfully in simulation but i am not able to do the same in
> the post synthesis scenario. More so I am getting a setup time
> violation for the same in the timing analysis . I am running the I2C
> at a very slow speed of 100KHz.
>
> The code is below
>
> process (SDA_IN, START_RST,rst)
> begin
> if rst ='1' then
> STARTOP <='0';
> -- elsif (START_RST = '1') then
> -- STARTOP <= '0';
> elsif (SDA_IN'event and SDA_IN = '0') then
> STARTOP <= scl;
> end if;
> end process;
> ------------------------------------------------------------------------------
> -- stop condition detection
> process (RST, SCL, SDA_IN, STARTOP)
> begin
> if RST = '1' or SCL = '0' or STARTOP='1' then
> STOPOP <= '0';
> elsif SDA_IN = '1' and SDA_IN'event then
> if SCL = '1' then
> STOPOP <= '1';
> end if ;
>
> end if;
> end process;
>
> Can any one give me a reliable way to detect the start and stop
> condition that the synthesis tool doesnot give any setup time
> violation. I am not using a high clock for sampling as the requirement
> is to use the SCL only. May be to save board resourse and space.
>
> Help will be appreciated. I am using Altera max II CPLD and the
> synthesis tool is quartus 9.0
>
> Thanks
>
> Vipul



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  #4 (permalink)  
Old 05-20-2009, 06:58 PM
VIPS
Guest
 
Posts: n/a
Default Re: i2c Start and stop detection

On May 19, 2:39*pm, "Brad Smallridge" <[email protected]>
wrote:
> Dear Vipul,
>
> Seems like you are always going to get
> some sort of timing issue since the rst
> signal and the SDA_IN signal are async.
>
> Propagating the STARTOP signal forward
> to the STOPOP reset circuitry also seems
> like a bad idea for some reason I can't
> quite articulate, except for an idea that
> the start and stop signals should be
> symetrical.
>
> If you have a system clock, I would suggest
> that you use registers at your SDA and SCL
> inputs right at the IOs. Then use old values
> of SDA and SCL to calculate your START and
> STOP signals:
>
> start_stop_procrocess(clk)
> begin
> if(clk'event and clk='1')then
> * STARTOP<='0';
> * STOPOP<='0';
> * SDA_1<=SDA_IN;
> * SDA_2<=SDA_1;
> * SCL_1<=SCL_IN;
> * if( SDA_1='0' and SDA_2='1' and SCL_1='1')then
> * *STARTOP<='1';
> * end if;
> * if( SDA_1='1' and SDA_2='0' and SCL_1='1')then
> * *STOPOP<='1';
> * end if;
> end if;
> end process;
>
> This should be very clean as long as your system clock
> and timing is OK. And it give clean oneshot reset signals
> for your address and data registers.
>
> Now if you are trying to run this from the SCL clock, perhaps
> just taking the rst out of your process may work, or putting
> it in the synchonous part of the block may work, and clean
> up the code so that the both signals look symetrical:
>
> start_procrocess(SDA_IN)
> begin
> *if(SDA_IN'event and SDA_IN='0')then
> * if(rst='1')then
> * *STARTOP<='0';
> * elsif(scl='1')then
> * *STARTOP<='1';
> * else
> * *STARTOP<='0';
> * end if;
> *end if;
> end process;
>
> stop_procrocess(SDA_IN)
> begin
> *if(SDA_IN'event and SDA_IN='1')then
> * if(rst='1')then
> * *STOPOP<='0';
> * elsif(scl='1')then
> * *STOPOP<='1';
> * else
> * *STOPOP<='0';
> * end if;
> *end if;
> end process;
>
> Then these signals need to be synched with scl clock
> signal before you start messing with your data registers.
> And you have to look for their edges since the SDA signal
> can drop and not come up if it's sending a zero datum.
>
> Using a system clock is a lot easier.
>
> I haven't ever done a I2C slave so you might get better
> answers elsewhere. Good luck.
>
> Brad Smallridge
> AiVision
>
> "VIPS" <[email protected]> wrote in message
>
> news:[email protected]m...
>
> > Hi all

>
> > I am implementing the I2C Slave and I am using the I2C clock SCL for
> > detecting the start and stop condition . I am detecting the start and
> > stop successfully in simulation but i am not able to do the same in
> > the post synthesis scenario. More so I am getting a setup time
> > violation for the same in the timing analysis . I am running the I2C
> > at a very slow speed of 100KHz.

>
> > The code is below

>
> > process (SDA_IN, START_RST,rst)
> > * begin
> > * * if rst ='1' then
> > * * * *STARTOP <='0';
> > * *-- elsif (START_RST = '1') then
> > * *-- * *STARTOP <= '0';
> > * * elsif (SDA_IN'event and SDA_IN = '0') then
> > * * * STARTOP <= scl;
> > * * end if;
> > * end process;
> > ------------------------------------------------------------------------------
> > -- stop condition detection
> > process (RST, SCL, SDA_IN, STARTOP)
> > begin
> > * *if RST = '1' or SCL = '0' or STARTOP='1' then
> > * * * *STOPOP <= '0';
> > * elsif *SDA_IN = '1' and SDA_IN'event then
> > * * * if SCL = '1' then
> > * * * * * * STOPOP <= '1';
> > * * * *end if ;

>
> > * end if;
> > *end process;

>
> > Can *any one give me a reliable way to detect the start and stop
> > condition that *the synthesis tool doesnot give any setup time
> > violation. I am not using a high clock for sampling as the requirement
> > is to use the SCL only. May be to save board resourse and space.

>
> > Help will be appreciated. I am using Altera max II CPLD and the
> > synthesis tool is quartus 9.0

>
> > Thanks

>
> > Vipul


Dear Brad

Thanks for your reply and for your time. Your suggestion is very
logical and I tried to implement it . The tool still gives an error in
the setup time though the slack reduced considerably . I will try to
work around it .
You have shown a good way to deal with it by making the two process
look symmetrical.
Thanks once again for your valuable time

Vipul
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  #5 (permalink)  
Old 05-20-2009, 09:44 PM
gabor
Guest
 
Posts: n/a
Default Re: i2c Start and stop detection

On May 20, 1:58*pm, VIPS <[email protected]> wrote:
> On May 19, 2:39*pm, "Brad Smallridge" <[email protected]>
> wrote:
>
>
>
> > Dear Vipul,

>
> > Seems like you are always going to get
> > some sort of timing issue since the rst
> > signal and the SDA_IN signal are async.

>
> > Propagating the STARTOP signal forward
> > to the STOPOP reset circuitry also seems
> > like a bad idea for some reason I can't
> > quite articulate, except for an idea that
> > the start and stop signals should be
> > symetrical.

>
> > If you have a system clock, I would suggest
> > that you use registers at your SDA and SCL
> > inputs right at the IOs. Then use old values
> > of SDA and SCL to calculate your START and
> > STOP signals:

>
> > start_stop_procrocess(clk)
> > begin
> > if(clk'event and clk='1')then
> > * STARTOP<='0';
> > * STOPOP<='0';
> > * SDA_1<=SDA_IN;
> > * SDA_2<=SDA_1;
> > * SCL_1<=SCL_IN;
> > * if( SDA_1='0' and SDA_2='1' and SCL_1='1')then
> > * *STARTOP<='1';
> > * end if;
> > * if( SDA_1='1' and SDA_2='0' and SCL_1='1')then
> > * *STOPOP<='1';
> > * end if;
> > end if;
> > end process;

>
> > This should be very clean as long as your system clock
> > and timing is OK. And it give clean oneshot reset signals
> > for your address and data registers.

>
> > Now if you are trying to run this from the SCL clock, perhaps
> > just taking the rst out of your process may work, or putting
> > it in the synchonous part of the block may work, and clean
> > up the code so that the both signals look symetrical:

>
> > start_procrocess(SDA_IN)
> > begin
> > *if(SDA_IN'event and SDA_IN='0')then
> > * if(rst='1')then
> > * *STARTOP<='0';
> > * elsif(scl='1')then
> > * *STARTOP<='1';
> > * else
> > * *STARTOP<='0';
> > * end if;
> > *end if;
> > end process;

>
> > stop_procrocess(SDA_IN)
> > begin
> > *if(SDA_IN'event and SDA_IN='1')then
> > * if(rst='1')then
> > * *STOPOP<='0';
> > * elsif(scl='1')then
> > * *STOPOP<='1';
> > * else
> > * *STOPOP<='0';
> > * end if;
> > *end if;
> > end process;

>
> > Then these signals need to be synched with scl clock
> > signal before you start messing with your data registers.
> > And you have to look for their edges since the SDA signal
> > can drop and not come up if it's sending a zero datum.

>
> > Using a system clock is a lot easier.

>
> > I haven't ever done a I2C slave so you might get better
> > answers elsewhere. Good luck.

>
> > Brad Smallridge
> > AiVision

>
> > "VIPS" <[email protected]> wrote in message

>
> >news:[email protected]m....

>
> > > Hi all

>
> > > I am implementing the I2C Slave and I am using the I2C clock SCL for
> > > detecting the start and stop condition . I am detecting the start and
> > > stop successfully in simulation but i am not able to do the same in
> > > the post synthesis scenario. More so I am getting a setup time
> > > violation for the same in the timing analysis . I am running the I2C
> > > at a very slow speed of 100KHz.

>
> > > The code is below

>
> > > process (SDA_IN, START_RST,rst)
> > > * begin
> > > * * if rst ='1' then
> > > * * * *STARTOP <='0';
> > > * *-- elsif (START_RST = '1') then
> > > * *-- * *STARTOP <= '0';
> > > * * elsif (SDA_IN'event and SDA_IN = '0') then
> > > * * * STARTOP <= scl;
> > > * * end if;
> > > * end process;
> > > ------------------------------------------------------------------------------
> > > -- stop condition detection
> > > process (RST, SCL, SDA_IN, STARTOP)
> > > begin
> > > * *if RST = '1' or SCL = '0' or STARTOP='1' then
> > > * * * *STOPOP <= '0';
> > > * elsif *SDA_IN = '1' and SDA_IN'event then
> > > * * * if SCL = '1' then
> > > * * * * * * STOPOP <= '1';
> > > * * * *end if ;

>
> > > * end if;
> > > *end process;

>
> > > Can *any one give me a reliable way to detect the start and stop
> > > condition that *the synthesis tool doesnot give any setup time
> > > violation. I am not using a high clock for sampling as the requirement
> > > is to use the SCL only. May be to save board resourse and space.

>
> > > Help will be appreciated. I am using Altera max II CPLD and the
> > > synthesis tool is quartus 9.0

>
> > > Thanks

>
> > > Vipul

>
> Dear Brad
>
> Thanks for your reply and for your time. Your suggestion is very
> logical and I tried to implement it . The tool still gives an error in
> the setup time though the slack reduced considerably . I will try to
> work around it .
> You have shown a good way to deal with it by making the two process
> look symmetrical.
> Thanks once again for your valuable time
>
> Vipul


Having implemented with many I2C slaves in my projects I would
like to add a few points:

1) If you don't want to sample the I2C signals with another
clock, you WILL need schmitt-trigger inputs on your device.
I2C rise times are very slow and can have a lot of noise
while transitioning through the threshold region of most
parts. Read the I2C spec to see the recommended hysteresis.
By the way, this is why you need level translators to go
from 3.3V to 5V I2C. The logic thresholds are ratiometric.

2) If you are using something like an FPGA without any
schmitt trigger inputs, you need to de-glitch the SCL
and SDA signals before you use them in your state machine.
This is due to the possibility of multiple transitions
being detected while the signal slowly rises through
the threshold region.

I have posted Verilog code for a simple I2C slave using
a higher speed clock and deglitching on the Xilinx forums.

Regards,
Gabor
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  #6 (permalink)  
Old 06-23-2009, 12:54 PM
Vikas
Guest
 
Posts: n/a
Default Re: i2c Start and stop detection

Gabour,
Should there be any relation between SYSTEM CLK and SCL if we have t
apply debouncing ckt?




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  #7 (permalink)  
Old 06-23-2009, 01:23 PM
Vikas
Guest
 
Posts: n/a
Default Re: i2c Start and stop detection

>Gabour,
>Should there be any relation between SYSTEM CLK and SCL if we have to
>apply debouncing ckt?
>
>
>
>
>


Gabor,
One more question. have u taken care of repeated start condition in th
above code?


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  #8 (permalink)  
Old 06-23-2009, 01:32 PM
gabor
Guest
 
Posts: n/a
Default Re: i2c Start and stop detection

On Jun 23, 7:54*am, "Vikas" <[email protected]> wrote:
> Gabour,
> Should there be any relation between SYSTEM CLK and SCL if we have to
> apply debouncing ckt?


Assuming that the system clock is much faster than SCL, there is no
need to assume any synchronization between the two. In fact the
rise time of SCL under worst case condition could span more than
one cycle of the system clock. This was the purpose of adding
the de-glitch circuit. In my code I used the same debounce /
de-glitch circuit for both SCL and SDA so the delays would be the
same going into the state machine.

Regards,
Gabor
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  #9 (permalink)  
Old 06-23-2009, 01:38 PM
gabor
Guest
 
Posts: n/a
Default Re: i2c Start and stop detection

On Jun 23, 8:23*am, "Vikas" <[email protected]> wrote:
> >Gabour,
> >Should there be any relation between SYSTEM CLK and SCL if we have to
> >apply debouncing ckt?

>
> Gabor,
> *One more question. have u taken care of repeated start condition in the
> above code?


The code makes no distinction between a normal start and a
repeated start. As far as I know it should work in either
case.

Regards,
Gabor
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  #10 (permalink)  
Old 06-23-2009, 02:08 PM
Andrew Holme
Guest
 
Posts: n/a
Default Re: i2c Start and stop detection

On 23 June, 13:32, gabor <[email protected]> wrote:
> On Jun 23, 7:54*am, "Vikas" <[email protected]> wrote:
>
> > Gabour,
> > Should there be any relation between SYSTEM CLK and SCL if we have to
> > apply debouncing ckt?

>
> Assuming that the system clock is much faster than SCL, there is no
> need to assume any synchronization between the two. *In fact the
> rise time of SCL under worst case condition could span more than
> one cycle of the system clock. *This was the purpose of adding
> the de-glitch circuit. *In my code I used the same debounce /
> de-glitch circuit for both SCL and SDA so the delays would be the
> same going into the state machine.
>
> Regards,
> Gabor


When the rise time is known, as it generally is, I use a sample period
approximately equal to the rise time. Then you don't need de-
glitching logic.
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  #11 (permalink)  
Old 06-24-2009, 06:49 AM
Vikas
Guest
 
Posts: n/a
Default Re: i2c Start and stop detection

>On 23 June, 13:32, gabor <[email protected]> wrote:
>> On Jun 23, 7:54=A0am, "Vikas" <[email protected]> wrote:
>>
>> > Gabour,
>> > Should there be any relation between SYSTEM CLK and SCL if we hav

to
>> > apply debouncing ckt?

>>
>> Assuming that the system clock is much faster than SCL, there is no
>> need to assume any synchronization between the two. =A0In fact the
>> rise time of SCL under worst case condition could span more than
>> one cycle of the system clock. =A0This was the purpose of adding
>> the de-glitch circuit. =A0In my code I used the same debounce /
>> de-glitch circuit for both SCL and SDA so the delays would be the
>> same going into the state machine.
>>
>> Regards,
>> Gabor

>
>When the rise time is known, as it generally is, I use a sample period
>approximately equal to the rise time. Then you don't need de-
>glitching logic.
>


Thanks for the Help Gabor!
Mine SCL frequency is 1 Mhz. What should be the frequency of system cloc
on which I should debounce it?Is 8 Mhz enough?


// Debounce, then delay debounced signals for edge detection
begin
sda_sr <= {sda_sr[2:0], sda_in};
if (sda_sr == 4'b0000) sda <= 0;
else if (sda_sr == 4'b1111) sda <= 1;
was_sda <= sda;
scl_sr <= {scl_sr[2:0], scl_in};
if (scl_sr == 4'b0000) scl <= 0;
else if (scl_sr == 4'b1111) scl <= 1;
was_scl <= scl;
end
One more doubt in above code.. Why r u checking for 0000 and 1111 value
only. As per me if the four bit registers hold three 1's, SDA should be
and if three bits are 0 then SDA should 0.
Can I have your Personal Email ID as well?
Thanks for the help sir!!!





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