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Old 11-28-2007, 08:11 AM
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Default I/O short circuit protection?

On the Spartan-3 with Vcco at 3.3V in LVTTL mode if I want to protect
the outputs from possible miswiring to GND or +3.3V or Output-2-
Output. Is there any common practice way to accomplish this?

I'm considering a 2.2k series resistor array "chip". But maybe there's
a more appropiate way?
Also what's the reaction of loading the output with say a 300 ohm
resistor and specifying 16 mA drive?
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Old 11-28-2007, 08:38 AM
Jim Granville
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Default Re: I/O short circuit protection?

[email protected] wrote:
> On the Spartan-3 with Vcco at 3.3V in LVTTL mode if I want to protect
> the outputs from possible miswiring to GND or +3.3V or Output-2-
> Output. Is there any common practice way to accomplish this?
>
> I'm considering a 2.2k series resistor array "chip". But maybe there's
> a more appropiate way?


Depends on your speed, and how rugged you want it.
2K2 would allow a fault to over +/- 24V, and still be OK.
You can parallel a cap, with each 2K2, if you need faster edges.

> Also what's the reaction of loading the output with say a 300 ohm
> resistor and specifying 16 mA drive?


If you have the choice, and a lot of drive loads, it can help to
avoid change of all drives at the same time. Reduces the ground bounce.

-jg

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Old 11-28-2007, 12:40 PM
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Default Re: I/O short circuit protection?

On Nov 28, 9:38 am, Jim Granville <[email protected]>
wrote:
> [email protected] wrote:
> > On the Spartan-3 with Vcco at 3.3V in LVTTL mode if I want to protect
> > the outputs from possible miswiring to GND or +3.3V or Output-2-
> > Output. Is there any common practice way to accomplish this?

>
> > I'm considering a 2.2k series resistor array "chip". But maybe there's
> > a more appropiate way?

>
> Depends on your speed, and how rugged you want it.
> 2K2 would allow a fault to over +/- 24V, and still be OK.
> You can parallel a cap, with each 2K2, if you need faster edges.
>
> > Also what's the reaction of loading the output with say a 300 ohm
> > resistor and specifying 16 mA drive?

>
> If you have the choice, and a lot of drive loads, it can help to
> avoid change of all drives at the same time. Reduces the ground bounce.


The other chips is an 10/100Mbps ethernet PHY (25 MHz/40ns).
And the concern is shorts to either GND or +3,3V (no 24V).
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Old 11-28-2007, 02:16 PM
John_H
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Default Re: I/O short circuit protection?

[email protected] wrote:
> On the Spartan-3 with Vcco at 3.3V in LVTTL mode if I want to protect
> the outputs from possible miswiring to GND or +3.3V or Output-2-
> Output. Is there any common practice way to accomplish this?
>
> I'm considering a 2.2k series resistor array "chip". But maybe there's
> a more appropiate way?
> Also what's the reaction of loading the output with say a 300 ohm
> resistor and specifying 16 mA drive?


Are you designing a board with a production run of three that you'll be
assembling with the toaster-oven technique?

If you're using a professional assembly house, there is post-assembly
testing that will test for shorts. If you have a production run too
small for a bed-of-nails tester, there are still flying-lead
manufacturing defect analyzers that can check your board for shorts.

Why design in "protection" that limits your signal characteristics when
all you're protecting from is manufacturing faults? If you were cycling
connecting the FPGA in and out of a connector over and over to varying
equipment, I could understand some concern. But for soldered-on chips?

There are better ways.
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Old 11-28-2007, 04:03 PM
David Spencer
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Default Re: I/O short circuit protection?


<[email protected]> wrote in message
news:[email protected]...
> On Nov 28, 9:38 am, Jim Granville <[email protected]>
> wrote:
>
> The other chips is an 10/100Mbps ethernet PHY (25 MHz/40ns).
> And the concern is shorts to either GND or +3,3V (no 24V).


Putting 2.2k series resistors in signals that will be expected to have rise
and fall times of one or two nanoseconds is very unlikely to work. Think
about it. The time constant of a 2.2k resistor in series with a 5pF input
capacitance is 11ns - an order of magnitude higher than your edge rate and
almost comparable to the actual cycle time.

As others have said, don't waste time designing for possible manufacturing
defects and compromising your design in the process. I would argue that the
only time you would do this is if a defect could cause major problems such
as fire or risk to life, neither of which is likely on a low-voltage,
low-power board.


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Old 11-29-2007, 02:14 AM
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Default Re: I/O short circuit protection?

On Nov 28, 3:16 pm, John_H <[email protected]> wrote:
> [email protected] wrote:


> Are you designing a board with a production run of three that you'll be
> assembling with the toaster-oven technique?
>
> If you're using a professional assembly house, there is post-assembly
> testing that will test for shorts. If you have a production run too
> small for a bed-of-nails tester, there are still flying-lead
> manufacturing defect analyzers that can check your board for shorts.
>
> Why design in "protection" that limits your signal characteristics when
> all you're protecting from is manufacturing faults? If you were cycling
> connecting the FPGA in and out of a connector over and over to varying
> equipment, I could understand some concern. But for soldered-on chips?


It's for a test setup, where I will test different fpga <-> device
setups. No production run at all, not even a prototype one.
I have bought a 100 ohm series resistor net package. Which will limit
any shorts to 33mA. And I think the rise times will be ok with this. t
= RC = 100*10pF (worst case Sp3E) = 1ns. The sp3e datasheet says max
100mA, I hope this will protect the fpga for those minutes it takes to
test the setup.

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