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Old 05-29-2009, 06:02 AM
Marteno Rodia
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Default I don't like xilinx (again)

Hello,
Again I encountered (or, more precisely, my colleague) some problem
with Xilinx. As far as I understand what he is trying to do, he wants
to synthesize two different cores into one system. The problem is that
during synthesis ISE throws out some pins of one core, which are,
however, necessary because they feeds inputs of the other core.

How could this happen? Any tips? What should we check?

MR
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  #2 (permalink)  
Old 05-29-2009, 06:42 AM
MM
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Default Re: I don't like xilinx (again)

1. The title of your message is not going to help you in resolving your
problem.
2. Your description of the problem is too generic. Generally speaking the
tools will throw out anything which is not required for final physical
output.


/Mikhail



"Marteno Rodia" <[email protected]> wrote in message
news:[email protected]..
> Hello,
> Again I encountered (or, more precisely, my colleague) some problem
> with Xilinx. As far as I understand what he is trying to do, he wants
> to synthesize two different cores into one system. The problem is that
> during synthesis ISE throws out some pins of one core, which are,
> however, necessary because they feeds inputs of the other core.
>
> How could this happen? Any tips? What should we check?
>
> MR



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  #3 (permalink)  
Old 05-29-2009, 07:22 PM
Mike Treseler
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Default Re: I don't like xilinx (again)

Marteno Rodia wrote:

> during synthesis ISE throws out some pins of one core, which are,
> however, necessary because they feeds inputs of the other core.
> How could this happen?


If both cores are instanced, you don't need pins
on the output of the first core.
To synthesize just one core, change the top entity/module.

-- Mike Treseler
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  #4 (permalink)  
Old 05-30-2009, 02:22 AM
KJ
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Default Re: I don't like xilinx (again)


"Marteno Rodia" <[email protected]> wrote in message
news:[email protected]..
> Hello,
> Again I encountered (or, more precisely, my colleague) some problem
> with Xilinx. As far as I understand what he is trying to do, he wants
> to synthesize two different cores into one system. The problem is that
> during synthesis ISE throws out some pins of one core, which are,
> however, necessary because they feeds inputs of the other core.
>
> How could this happen?


If some (or all) of the outputs of core #2 do not make it to physical output
pins of the device then it is quite possible that some of the inputs to core
#2 can disappear. If those core #2 inputs happen to come from outputs of
core #1 and those signals do not happen to go anywhere else, those will get
optimized away as well.

To put it more simply, those signals between core #1 and #2 that you think
'should' be there, do not in fact effect the value of any physical I/O pins
of the device...therefore they can be removed and the behaviour of the
device will not be affected. Second guessing the synthesis tool is usually
a pointless exercise, the tool is correct in it's analysis of your logic
very, very often.

> Any tips?


Run a simulation of the whole design.

> What should we check?
>

That the output of the simulation matches what you expect.

As 'MM' pointed out, the subject line of your post will not help
you...consider not slamming others just because of your frustration.

Kevin Jennings


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  #5 (permalink)  
Old 05-30-2009, 06:16 AM
Guest
 
Posts: n/a
Default Re: I don't like xilinx (again)

Considering a lot of xilinx employees post on this group, it's
probably not too smart to tell somebody you don't like them and then
expect that same person to help you. Just my $0.02.

On May 29, 6:22*pm, "KJ" <[email protected]> wrote:
> "Marteno Rodia" <[email protected]> wrote in message
>
> news:[email protected]..
>
> > Hello,
> > Again I encountered (or, more precisely, my colleague) some problem
> > with Xilinx. As far as I understand what he is trying to do, he wants
> > to synthesize two different cores into one system. The problem is that
> > during synthesis ISE throws out some pins of one core, which are,
> > however, necessary because they feeds inputs of the other core.

>
> > How could this happen?

>
> If some (or all) of the outputs of core #2 do not make it to physical output
> pins of the device then it is quite possible that some of the inputs to core
> #2 can disappear. *If those core #2 inputs happen to come from outputs of
> core #1 and those signals do not happen to go anywhere else, those will get
> optimized away as well.
>
> To put it more simply, those signals between core #1 and #2 that you think
> 'should' be there, do not in fact effect the value of any physical I/O pins
> of the device...therefore they can be removed and the behaviour of the
> device will not be affected. *Second guessing the synthesis tool is usually
> a pointless exercise, the tool is correct in it's analysis of your logic
> very, very often.
>
> > Any tips?

>
> Run a simulation of the whole design.
>
> > What should we check?

>
> That the output of the simulation matches what you expect.
>
> As 'MM' pointed out, the subject line of your post will not help
> you...consider not slamming others just because of your frustration.
>
> Kevin Jennings


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  #6 (permalink)  
Old 06-02-2009, 07:21 AM
Marteno Rodia
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Posts: n/a
Default Re: I don't like xilinx (again)

Thank you - you're right, it's highly improfessional to let my
frustration be shown... But I was really frustrated! I still don't
like Xilinx, but now I'm saying this for the last time. At least,
while asking for help.

MR
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