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  #1 (permalink)  
Old 10-27-2007, 06:32 AM
motty
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Default How to use an internal signal in a testbench...

I am simulating an EDK system and want to use some internal signals at
the testbench level (without routing them up to external ports). I
thought that you could simply do this by assigning signals using
hierachry nomenclature. For a specific example, I want to use the
clk0 output of a DCM as a clock at the testbench level. I have tried
the following:

wire clk_150_mhz = system_tb.system.dcm_1.dcm_1.clk0
In ModelSim PE I get an error that clk0 could not be found in the
hierarchy.

wire clk_150_mhz = ".system_tb.system.dcm_1.dcm_1.clk0"
ModelSim does NOT give an error, but the signal is always static 0.
The dcm clock is definitely toggling, by the way.

wire clk_150_mhz = "/system_tb/system/dcm_1/dcm_1/clk0"
Same as above.

This is supposedly the correct hiearchy. I compiled and vsim'ed the
design without trying to connect the lower level signal so I could get
a working simulation. I then added the dcm_1 clk0 signal waveform to
the window and the hierarchy was system_tb/system/dcm_1/dcm_1/clk0.

So what am I missing? This should be simple and I am grinding my
gears here!

Thanks in advance!!

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  #2 (permalink)  
Old 10-27-2007, 09:47 AM
Jonathan Bromley
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Default Re: How to use an internal signal in a testbench...

On Fri, 26 Oct 2007 22:32:18 -0700, motty <[email protected]>
wrote:

>I am simulating an EDK system and want to use some internal signals at
>the testbench level (without routing them up to external ports). I
>thought that you could simply do this by assigning signals using
>hierachry nomenclature. For a specific example, I want to use the
>clk0 output of a DCM as a clock at the testbench level. I have tried
>the following:
>
>wire clk_150_mhz = system_tb.system.dcm_1.dcm_1.clk0


Your design and testbench are all in Verilog, right?

>In ModelSim PE I get an error that clk0 could not be found in the
>hierarchy.


Apart from the missing semicolon at the end of the
wire assignment, this is perfectly valid Verilog; so
I suspect ModelSim is right, and you have made some
small error in the hierarchical name. Case sensitivity?
> wire clk_150_mhz = ".system_tb.system.dcm_1.dcm_1.clk0"
>ModelSim does NOT give an error, but the signal is always static 0.


Yeah. The string is a very wide Verilog constant; because its
last character is '0', whose ASCII code is an even number,
your single-bit wire will be jammed to zero.

The leading '.' would be wrong in any case.

>wire clk_150_mhz = "/system_tb/system/dcm_1/dcm_1/clk0"
>Same as above.


Same reason: you've assigned a 34-character string,
which is an 8*34-bit constant vector, to the wire.
Its LSB happens to be zero, so that's what you get.

The slashes would never work in a Verilog hierarchical name.

>This is supposedly the correct hiearchy. I compiled and vsim'ed the
>design without trying to connect the lower level signal so I could get
>a working simulation. I then added the dcm_1 clk0 signal waveform to
>the window and the hierarchy was system_tb/system/dcm_1/dcm_1/clk0.
>
>So what am I missing? This should be simple and I am grinding my
>gears here!


That all sounds correct. Sanity check: this is *really* all in
Verilog, right? Every level of the hierarchy? And that
hierarchical path really is starting from the very top of your
hierarchy?

Here's another thought: Can you, temporarily, patch the code
of the lowest level of the hierarchy - the place where
"clk0" lives? If so, put this code right next to the
declaration of "clk0" (or, if it's a port, somewhere
inside the module that has it as a port):

initial $display(" The signal I want is at %m ");

The %m formatter will display the full Verilog hierarchy
path to that point in the design. Add ".clk0" to the
end of that name, and that's your signal name.

If all else fails, look at the ModelSim docs for "SignalSpy".
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
[email protected]
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.


>Thanks in advance!!

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  #3 (permalink)  
Old 10-27-2007, 04:59 PM
motty
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Default Re: How to use an internal signal in a testbench...

Thanks Jonathan,

The project is NOT all in Verilog. The EDK uses VHDL wrappers for all
the modules and I am using Xilinx IP cores which are written in VHDL.
The testbench and the system are in Verilog. Underneath that level
are all VHDL wrappers. Some modules inside the wrappers are Verilog
and some are VHDL. I have pointed ModelSim to the unisims_ver library
which contains the Xilinx primitves in Verilog. I am pretty sure the
DCM model would be used from here so it should be Verilog, but again,
its wrapper is in VHDL.

Is there some trick when you traverse hierarchy of diferent
languages?

I did try to use signal spy, but it didn't work either. It produced
either a static 0 signal or a static z signal, but I may revisit that
to see if I was doing things incorrectly...which is quite possible!

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  #4 (permalink)  
Old 10-27-2007, 05:25 PM
Jonathan Bromley
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Posts: n/a
Default Re: How to use an internal signal in a testbench...

On Sat, 27 Oct 2007 08:59:30 -0700, motty <[email protected]>
wrote:

>Thanks Jonathan,
>
>The project is NOT all in Verilog. The EDK uses VHDL wrappers for all
>the modules and I am using Xilinx IP cores which are written in VHDL.
>The testbench and the system are in Verilog. Underneath that level
>are all VHDL wrappers. Some modules inside the wrappers are Verilog
>and some are VHDL. I have pointed ModelSim to the unisims_ver library
>which contains the Xilinx primitves in Verilog. I am pretty sure the
>DCM model would be used from here so it should be Verilog, but again,
>its wrapper is in VHDL.


I think that's the problem; I don't believe you can read "through"
a VHDL wrapper, not even into a Verilog lower-level module.
But I could be wrong - it's a while since I played with that
sort of thing in ModelSim.

>Is there some trick when you traverse hierarchy of diferent
>languages?


Probably, but it might be worth asking your Mentor AE or
distributor...

>I did try to use signal spy, but it didn't work either. It produced
>either a static 0 signal or a static z signal, but I may revisit that
>to see if I was doing things incorrectly...which is quite possible!


Again, I don't know enough about SignalSpy to be sure what happens
in a mixed-language environment, but I *thought* it could see
anything the simulator can see. Probably a case of RTFM carefully
(again). Good luck.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
[email protected]
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
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