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Old 04-21-2006, 06:18 AM
srini
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Default How to trsiate o/p pins?

Hi,
I am new to designing with FPGAs. I have an enable_output pin in my
FPGA which if deasserted will make the o/p data pins(32 pins) to Hi-Z
state. I would like to know how to make these o/p pins as Hi-Z by using
the control input (i.e) enable_output. I using Verilog and Synplify Pro
for synthesis and Xilinx ISE7.1 for PAR.

Thanks & Regards,
Srini.

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Old 04-21-2006, 09:12 AM
Martin Thompson
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Default Re: How to trsiate o/p pins?

"srini" <[email protected]> writes:

> Hi,
> I am new to designing with FPGAs. I have an enable_output pin in my
> FPGA which if deasserted will make the o/p data pins(32 pins) to Hi-Z
> state. I would like to know how to make these o/p pins as Hi-Z by using
> the control input (i.e) enable_output. I using Verilog and Synplify Pro
> for synthesis and Xilinx ISE7.1 for PAR.
>


It's straightforward in VHDL:

buspins <= value when OE = '1' lese (others => 'Z');

I guess in verilog it's something like:

assign buspins = (OE) ? drive : 32'bz;

but I'm not a verilog expert.

I'm sure the Synplify help tells you all about inferring tristate
pins, but I can't find it myself :-(

Cheers,

Martin


--
[email protected]
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.trw.com/conekt

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  #3 (permalink)  
Old 04-21-2006, 01:57 PM
Gabor
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Default Re: How to trsiate o/p pins?


Martin Thompson wrote:
> "srini" <[email protected]> writes:
>
> > Hi,
> > I am new to designing with FPGAs. I have an enable_output pin in my
> > FPGA which if deasserted will make the o/p data pins(32 pins) to Hi-Z
> > state. I would like to know how to make these o/p pins as Hi-Z by using
> > the control input (i.e) enable_output. I using Verilog and Synplify Pro
> > for synthesis and Xilinx ISE7.1 for PAR.
> >

>
> It's straightforward in VHDL:
>
> buspins <= value when OE = '1' else (others => 'Z');
>
> I guess in verilog it's something like:
>
> assign buspins = (OE) ? drive : 32'bz;


To be equivalent to VHDL code it would be

assign buspins = OE ? value : 32'bz;

(parentheses are not required)

>
> but I'm not a verilog expert.
>
> I'm sure the Synplify help tells you all about inferring tristate
> pins, but I can't find it myself :-(
>
> Cheers,
>
> Martin
>
>
> --
> [email protected]
> TRW Conekt - Consultancy in Engineering, Knowledge and Technology
> http://www.trw.com/conekt


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