FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 06-09-2008, 09:02 PM
Andy Botterill
Guest
 
Posts: n/a
Default how to track down an optimised away signal

Using verilog and ISE 10.1.

I add a reg to modify the design's behaviour. It works and it works
correctly. The change is intended to invert the carry logic for some
op-codes.

However synthesis , using XST , gives the following warning message.

WARNING:Xst:646 - Signal <borrow> is assigned but never used. This
unconnected signal will be trimmed during the optimization process.

What I would like to do is to find out which lines are caing this
warning and see if I have missed something or the synthesis tool has
made a mistake.

All sixteen op-codes assign something to borrow. Sometimes true,
sometimes inverse and sometimes 0.

I added a KEEP statement to the reg and of course everything was OK.
When I added a KEEP statement to each line that assigned to the reg
borrow I got the abover warning message.

Is there any synthesis qualifiers which say presevre the nets in this
line only?

Thanks for any advice andy.
Reply With Quote
  #2 (permalink)  
Old 06-09-2008, 09:10 PM
Mike Treseler
Guest
 
Posts: n/a
Default Re: how to track down an optimised away signal

Andy Botterill wrote:

> WARNING:Xst:646 - Signal <borrow> is assigned but never used. This
> unconnected signal will be trimmed during the optimization process.
>
> What I would like to do is to find out which lines are caing this
> warning and see if I have missed something or the synthesis tool has
> made a mistake.


It is most likely a logical error in the code.

> All sixteen op-codes assign something to borrow. Sometimes true,
> sometimes inverse and sometimes 0.


OK, but what xst is claiming is that
no register is being assigned *to* by
the "borrow" register.

In other words, "borrow" does not appear
on the right side of any active assignment
that affects a top port output..

-- Mike Treseler
Reply With Quote
  #3 (permalink)  
Old 06-09-2008, 09:40 PM
Andy Botterill
Guest
 
Posts: n/a
Default Re: how to track down an optimised away signal

Mike Treseler wrote:
> Andy Botterill wrote:
>
>
>>WARNING:Xst:646 - Signal <borrow> is assigned but never used. This
>>unconnected signal will be trimmed during the optimization process.
>>
>>What I would like to do is to find out which lines are caing this
>>warning and see if I have missed something or the synthesis tool has
>>made a mistake.

>
>
> It is most likely a logical error in the code.

I agree with that I'm trying to figure out how to track it down.
>
>
>>All sixteen op-codes assign something to borrow. Sometimes true,
>>sometimes inverse and sometimes 0.

>
>
> OK, but what xst is claiming is that
> no register is being assigned *to* by
> the "borrow" register.


(* KEEP = "TRUE" *){borrow, Rd_contents}=Rn_contents - shifter_operand;
There are at least three occurences similar to above.
Some are assigned to zero which may give the synthesis tool the idea
that it could be optimised.

>
> In other words, "borrow" does not appear
> on the right side of any active assignment
> that affects a top port output..


borrow does not go to a top level port but it is used in the carry logic
which goes to a primary output.
>
> -- Mike Treseler

Reply With Quote
  #4 (permalink)  
Old 06-09-2008, 09:51 PM
Mike Treseler
Guest
 
Posts: n/a
Default Re: how to track down an optimised away signal

Andy Botterill wrote:

> (* KEEP = "TRUE" *){borrow, Rd_contents}=Rn_contents - shifter_operand;


^ that's on the left side.

Borrow is being updated, not used, in that assignment.

> There are at least three occurrences similar to above.


It doesn't matter how many there are.

> Some are assigned to zero which may give the synthesis tool the idea
> that it could be optimised.


Unless there is an assignment like

my_top_port <= some_function_of_borrow;

Then synthesis is correct in removing the register.
I would run a sim to see what is really going on.

-- Mike Treseler
Reply With Quote
  #5 (permalink)  
Old 06-09-2008, 10:10 PM
Symon
Guest
 
Posts: n/a
Default Re: how to track down an optimised away signal

Andy Botterill wrote:
> Using verilog and ISE 10.1.
>
> I add a reg to modify the design's behaviour. It works and it works
> correctly. The change is intended to invert the carry logic for some
> op-codes.
>
> However synthesis , using XST , gives the following warning message.
>
> WARNING:Xst:646 - Signal <borrow> is assigned but never used. This
> unconnected signal will be trimmed during the optimization process.
>

Hi Andy,
Do you have a signal such as 'carry' which is the exact inverse of 'borrow'?
I.e. borrow = not carry? If you do, the synthesis tool might optimise
'borrow' away and use carry throughout.
HTH., Syms.


Reply With Quote
  #6 (permalink)  
Old 06-10-2008, 04:43 PM
Muzaffer Kal
Guest
 
Posts: n/a
Default Re: how to track down an optimised away signal

On Mon, 09 Jun 2008 21:02:25 +0100, Andy Botterill
<[email protected]> wrote:

>Using verilog and ISE 10.1.
>
>I add a reg to modify the design's behaviour. It works and it works
>correctly. The change is intended to invert the carry logic for some
>op-codes.
>
>However synthesis , using XST , gives the following warning message.
>
>WARNING:Xst:646 - Signal <borrow> is assigned but never used. This
>unconnected signal will be trimmed during the optimization process.
>
>What I would like to do is to find out which lines are caing this
>warning and see if I have missed something or the synthesis tool has
>made a mistake.
>
>All sixteen op-codes assign something to borrow. Sometimes true,
>sometimes inverse and sometimes 0.


What do you do with borrow? The synthesis tool is complaining that you
don't use "borrow" not that you don't assign to it. You can store the
borrow net's value in a register and use it in later instructions.
That way it can not be optimized away. Are you sure borrow is being
used ie, it is on the right side of an assignment? Also remember that
if you're using borrow in combinational logic and it's a real inverse
of carry, as someone else already pointed out, you may not need borrow
at all. Investigate how borrow is used.
Reply With Quote
  #7 (permalink)  
Old 06-10-2008, 08:58 PM
Andy Botterill
Guest
 
Posts: n/a
Default Re: how to track down an optimised away signal

Muzaffer Kal wrote:

>
> What do you do with borrow? The synthesis tool is complaining that you
> don't use "borrow" not that you don't assign to it. You can store the
> borrow net's value in a register and use it in later instructions.
> That way it can not be optimized away. Are you sure borrow is being
> used ie, it is on the right side of an assignment? Also remember that
> if you're using borrow in combinational logic and it's a real inverse
> of carry, as someone else already pointed out, you may not need borrow
> at all. Investigate how borrow is used.


I think I have figured it out.

I have 3 adders which use the MSB as a carry which is unchanged and
assigned to COm.

I have 5 subtractors which use the MSB as a borrow out. CCOm is the
inverse of borrow.

The other op-codes do not change borrow or carry. They haven'nt been
finished yet.

I think that the inversion logic has been pushed inside the subtractor
circuit. I tried to do this explicitly a bit like
{~COm, Rd_contents}=Rn_contents - shifter_operand;

It's not legal syntax. Using the ! operator equally doesn't work.

I'll go away and have a think.

The simulation does exactly what I want.

Reply With Quote
  #8 (permalink)  
Old 06-10-2008, 09:12 PM
Mike Treseler
Guest
 
Posts: n/a
Default Re: how to track down an optimised away signal

Andy Botterill wrote:

> I think that the inversion logic has been pushed inside the subtractor
> circuit.


> I'll go away and have a think.
> The simulation does exactly what I want.


Since the sim is ok, and synthesis is error free,
I would bet a tank of gas that synthesis got it right.

Rather than using brain cycles on manual
synthesis, I would either

1. Bring "carry" out to a testpoint pin and have
a look at the rtl schematic to settle the question, or

2. Assume synthesis is ok and finish the design.

-- Mike Treseler
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
ANNOUNCE: Fast-Track course on Verification Using SystemVerilog -Bangalore [email protected] Verilog 0 06-02-2008 06:14 PM
How to make an internal signal embedded deep in hierarchy to a gloal output signal Weng Tianxiang FPGA 10 01-30-2007 06:14 AM
Will this DCM cascade track a frequency offset clock? Ken FPGA 3 05-10-2005 07:59 AM
Altera Quartus Error How to track donw. GMM50 FPGA 5 01-09-2005 02:16 AM
CfP - Track on EMBEDDED SYSTEMS at ACM SAC 2005 Alessio Bechini FPGA 0 07-05-2004 03:04 PM


All times are GMT +1. The time now is 11:57 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2024, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved