FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 01-05-2004, 11:19 AM
chi
Guest
 
Posts: n/a
Default how to set the ISP mode for programming CPLD?

Hello,


I need to program CoolRunner CPLD using an embedded controller. How to
set the CPLD registers to work in the ISP mode?

Please explain how to do.

Regards,
Chi
Reply With Quote
  #2 (permalink)  
Old 01-05-2004, 11:46 AM
Amontec Team, Laurent Gauch
Guest
 
Posts: n/a
Default Re: how to set the ISP mode for programming CPLD?

chi wrote:
> Hello,
>
>
> I need to program CoolRunner CPLD using an embedded controller. How to
> set the CPLD registers to work in the ISP mode?
>
> Please explain how to do.
>
> Regards,
> Chi

just put PORT_EN pin to '1' !

Laurent Gauch
www.amontec.com

Reply With Quote
  #3 (permalink)  
Old 01-19-2004, 03:04 PM
chi
Guest
 
Posts: n/a
Default Re: how to set the ISP mode for programming CPLD?

"Amontec Team, Laurent Gauch" <[email protected]> wrote in message news:<[email protected]>.. .
> chi wrote:
> > Hello,
> >
> >
> > I need to program CoolRunner CPLD using an embedded controller. How to
> > set the CPLD registers to work in the ISP mode?
> >
> > Please explain how to do.
> >
> > Regards,
> > Chi

> just put PORT_EN pin to '1' !
>
> Laurent Gauch
> www.amontec.com


1. In My design PORT_EN pin is connected to ground. Is it possible to
enable ISP mode through instruction ISPEN command?


thanks and regards
Chi
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Programming Xilinx CPLD under linux James FPGA 8 09-09-2003 09:29 PM
Atmel CPLD programming tools Roger FPGA 1 08-11-2003 06:43 AM


All times are GMT +1. The time now is 10:09 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved