Paul wrote:
> hi, there,
>
> I want to set one of I/O pin as 3 state, how can I do this in Xilinx
> FPGA using Verilog?
>
> thanks
You may want to ask in comp.lang.verilog.
VHDL code:
-- this makes the output "out_pin" hi-impedance when "Z_enable" is a
'1'.
-- Otherwise, "out_pin" is assigned the value of "some_bit".
out_pin <= 'Z' when Z_enable = '1'
else some_bit;
HTH
-Dave Pollum