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Old 05-04-2006, 07:50 PM
Paul
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Default how to set a I/O as 3-state in xilinx FPGA?

hi, there,

I want to set one of I/O pin as 3 state, how can I do this in Xilinx
FPGA using Verilog?

thanks

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Old 05-04-2006, 11:25 PM
Dave Pollum
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Default Re: how to set a I/O as 3-state in xilinx FPGA?

Paul wrote:
> hi, there,
>
> I want to set one of I/O pin as 3 state, how can I do this in Xilinx
> FPGA using Verilog?
>
> thanks


You may want to ask in comp.lang.verilog.

VHDL code:
-- this makes the output "out_pin" hi-impedance when "Z_enable" is a
'1'.
-- Otherwise, "out_pin" is assigned the value of "some_bit".
out_pin <= 'Z' when Z_enable = '1'
else some_bit;
HTH
-Dave Pollum

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  #3 (permalink)  
Old 05-07-2006, 07:22 AM
Alif Wahid
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Default Re: how to set a I/O as 3-state in xilinx FPGA?

Dave Pollum wrote:
> Paul wrote:
>> hi, there,
>>
>> I want to set one of I/O pin as 3 state, how can I do this in Xilinx
>> FPGA using Verilog?
>>
>> thanks

>
> You may want to ask in comp.lang.verilog.
>
> VHDL code:
> -- this makes the output "out_pin" hi-impedance when "Z_enable" is a
> '1'.
> -- Otherwise, "out_pin" is assigned the value of "some_bit".
> out_pin <= 'Z' when Z_enable = '1'
> else some_bit;


Moreover, you may need to constrain that pin as a tristate driver by
explicitly specifying that to your synthesis tool outside of VHDL.

Regards,

Alif.

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