FPGA Central

My altera FPGA is connected to a SDRAM on the prototype board.
Assume the clock frequency is 100MHz, how much margin should I
give to the SDRAM? 3ns? 5ns?

news reader wrote:
> My altera FPGA is connected to a SDRAM on the prototype board.
> Assume the clock frequency is 100MHz, how much margin should I
> give to the SDRAM? 3ns? 5ns?

Huh?

Read your DRAM's specs and arrange your FPGA's timings to meet your
particular DRAM's setup and hold times just like you should already be
doing for any other external IC... or any clocked component for that matter.

"Daniel S." <[email protected]> wrote in message
news:[email protected]...
> news reader wrote:
>> My altera FPGA is connected to a SDRAM on the prototype board.
>> Assume the clock frequency is 100MHz, how much margin should I
>> give to the SDRAM? 3ns? 5ns?
>
> Huh?
>
> Read your DRAM's specs and arrange your FPGA's timings to meet your
> particular DRAM's setup and hold times just like you should already be
> doing for any other external IC... or any clocked component for that
> matter.

assume the SDRAM is 133MHz type, and my FPGA system design clock is 90MHz.
During simulation I use 10ns clock, and timing satisfied. Will it guarantee
that the system
will work after setup/hold time is satisfied?

For a large board with 133MHz SDRAM and FPGA, what are the approx. range of
interconnect delays between FPGA pins and SDRAM pins?

"news reader" <[email protected]> wrote in message
news:[email protected]...
>
> For a large board with 133MHz SDRAM and FPGA, what are the approx. range
> of
> interconnect delays between FPGA pins and SDRAM pins?
>
Hi News,
You should learn how to Google! ;-)
propagation delay trace
HTH, Syms.