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Old 04-19-2006, 03:14 AM
Ken Reeves
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Default How is the max clock rate of a device fixed?

Hi,

I'd like to know how a manufacturer arrives at the max clock rate of a
particular speed grade of a device? For example, if we have the Xilinx
Virtex-II Pro XC2VP50 FPGA with speed grade 7 parts, how's the max limit
of 200 MHz fixed? If I build a design for which I make sure that all
stages complete under, say 4ns, for the XC2VP50, I would benefit if I
can clock the FPGA at 250 MHz. What issues would prevent a higher clock
rate from being allowed?

Also, if it's based on various calculations, how do you end up with so
round figures as 200 MHz or 400 MHz?

Thanks.
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Old 04-19-2006, 05:12 AM
Peter Alfke
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Default Re: How is the max clock rate of a device fixed?

Just ignore that number of Fmax, if your timing simulation tells you
that the clock period can be shorter.
Watch the max output frequency of the DCM though.
Peter Alfke, Xilinx Applications

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Old 04-19-2006, 10:33 AM
Symon
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Default Re: How is the max clock rate of a device fixed?

IIRC the Fmax number is something made up by companies to satisfy government
export control licenses. Above a certain toggle rate it's illegal to ship to
'evil' countries. Although that might be nonsense.
Cheers, Syms.
"Peter Alfke" <[email protected]> wrote in message
news:[email protected] oups.com...
> Just ignore that number of Fmax, if your timing simulation tells you
> that the clock period can be shorter.
> Watch the max output frequency of the DCM though.
> Peter Alfke, Xilinx Applications
>



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Old 04-19-2006, 12:04 PM
Rene Tschaggelar
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Default Re: How is the max clock rate of a device fixed?

Ken Reeves wrote:

> Hi,
>
> I'd like to know how a manufacturer arrives at the max clock rate of a
> particular speed grade of a device? For example, if we have the Xilinx
> Virtex-II Pro XC2VP50 FPGA with speed grade 7 parts, how's the max limit
> of 200 MHz fixed? If I build a design for which I make sure that all
> stages complete under, say 4ns, for the XC2VP50, I would benefit if I
> can clock the FPGA at 250 MHz. What issues would prevent a higher clock
> rate from being allowed?
>
> Also, if it's based on various calculations, how do you end up with so
> round figures as 200 MHz or 400 MHz?



There have to be some timing cathegories, thus the
round numbers. Ever wondered why resistors are
available in 1%, 5%, 10% margin, that is the same.

And while your board may only be used at lab
conditions, the specified timing is met in the full
temperature range, the full supply voltage range(s).
Meaning, the specified timing is met at for the chip
worst case.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net
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Old 04-19-2006, 04:37 PM
John_H
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Default Re: How is the max clock rate of a device fixed?

The DCM output is specified up to 450 MHz.
The maximum PowerPC clock is 400 MHz.
The "Toggle Frequency (for export control)" is 1050 MHz.
Minimum clock period to meet address write cycle time is specified as 1.25
ns (800 MHz).
Where do you find 200 MHz as a limit of this silicon from the data sheet?

"Ken Reeves" <[email protected]> wrote in message
news:[email protected]
> Hi,
>
> I'd like to know how a manufacturer arrives at the max clock rate of a
> particular speed grade of a device? For example, if we have the Xilinx
> Virtex-II Pro XC2VP50 FPGA with speed grade 7 parts, how's the max limit
> of 200 MHz fixed? If I build a design for which I make sure that all
> stages complete under, say 4ns, for the XC2VP50, I would benefit if I can
> clock the FPGA at 250 MHz. What issues would prevent a higher clock rate
> from being allowed?
>
> Also, if it's based on various calculations, how do you end up with so
> round figures as 200 MHz or 400 MHz?
>
> Thanks.



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