FPGA Groups

FPGA Groups (http://www.fpgacentral.com/group/index.php)
-   FPGA (http://www.fpgacentral.com/group/forumdisplay.php?f=14)
-   -   how to make ports visible? (http://www.fpgacentral.com/group/showthread.php?t=63199)

xenix 11-13-2007 02:41 PM

how to make ports visible?
 
Hello all,

I am trying to make the PORT B of a BRAM visible in EDK ver.6.2i .
The only ports can make visible from PORT B is only the CLK.

have you any idea how to do the rest ports of BRAM PORT B visible?

regards


roger 11-13-2007 11:42 PM

Re: how to make ports visible?
 
On Nov 13, 2:41 pm, xenix <[email protected]> wrote:
> Hello all,
>
> I am trying to make the PORT B of a BRAM visible in EDK ver.6.2i .
> The only ports can make visible from PORT B is only the CLK.
>
> have you any idea how to do the rest ports of BRAM PORT B visible?
>
> regards


Hi!

Do you mean that you want port B of a BRAM possible to connect to as
independent ports and not a bus interface? In that case make a copy of
the file bram_block_v2_1_0.mpd in the $EDK/hw/XilinxProcessorIPLib/
pcores/bram_block_v1_00_a/data folder and rename it for example
bram_block_modified.mpd. Remove the BUS = PORTB and the default
connections of the signals, i.e. instead of BRAM_Dout_B = BRAM_Dout
insert BRAM_Dout_B = "". Add the mpd file to the user repository of
EDK and then you might have to restart XPS. Add the modified file to
your project and now port B of the bram will be visible in the port
connections. I have done this in later versions of EDK, hopefully it
will work in 6.2 as well.

Regards,
Roger



All times are GMT +1. The time now is 01:44 AM.

Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved