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How to handle top-level glue logic.

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01-19-2004, 09:19 AM

Kelvin @ SG

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How to handle top-level glue logic.

Hi, there:

I have fixed module A (right) and reconfigurable module B & C(left), the
clock buffers are all A's resource area.
I need a local constant vcc_fake to control the BUFGMUX. However, my
available IOs are only on the right-side
of the FPGA, meaning the vcc_fake travels diagonally from the right-middle
to the top-middle of the chip,
and across the fixed module A's allocated area...

In active-module implementation, I found the routing of this vcc_fake
between A and B/C are different now. What
will happen in the final assembly? Which routing will PAR adopt in the final
assembly?

Thanks for your advice.
Kelvin

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