FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 12-25-2003, 03:56 PM
Newhand
Guest
 
Posts: n/a
Default How to get first bit '0' position in certain register?

Dear all,

For certain register, say stream = 16'b1111010011111111;
the position of first bit '0' is: 8 (from LSB);
if stream = 16'b1111000100010011, then the position is 2;

what I need is to get the position.

Since it should be done in one clock cycle, combination logic in
Verilog might be a better choice.

Could anybody give me some pieces of suggestion? Thanks in advance.

Newhand
Reply With Quote
  #2 (permalink)  
Old 12-26-2003, 12:45 AM
Martin Euredjian
Guest
 
Posts: n/a
Default Re: How to get first bit '0' position in certain register?

"Newhand" wrote:

> For certain register, say stream = 16'b1111010011111111;
> the position of first bit '0' is: 8 (from LSB);
> if stream = 16'b1111000100010011, then the position is 2;
>
> what I need is to get the position.
>
> Since it should be done in one clock cycle, combination logic in
> Verilog might be a better choice.
>
> Could anybody give me some pieces of suggestion? Thanks in advance.



Two possible approaches:

1) Priority encoder


always @(posedge CLOCK)begin
if(~A[0]) OUT <= 4'd0;
else if(~A[1]) OUT <= 4'b1;
else if(~A[2]) OUT <= 4'b2;
... // etc., etc.
end


2) Counter

The basic idea is simple: If your operating clock is slow enough, generate a
16x clock by whatever means your device allows. On every 1x clock, start a
counter at 16x and stop it when the first "0" is found.



--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
[email protected]
where
"0_0_0_0_" = "martineu"


Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Trying to monitor output of a register instantiates another register seanadams Verilog 1 02-11-2004 07:13 PM
Transforming vector position to binary value Vazquez FPGA 23 11-20-2003 03:00 AM


All times are GMT +1. The time now is 09:13 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved