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Old 04-23-2009, 07:50 PM
Andy Botterill
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Default how to create multiple gatelevel files from multiple rtl files duringsynthesis

When I started this project I only had one file in the prject I got used
to the convention of
a.v creating a_timesim.v
creating a_synthesis.v
creating a_timesim.sdf

Now that I have 3 modules designed and in separate files I would like to
continue the above convention.

When I ticked the Generate Multiple Hierarchical Netlist files button I got
a,v creates a_a_sim.v
b.v creates b_synthese.v

Is there any way of continuing the first naming convention. Do I need a
different synthesis option or to write a tcl script to do it? Thanks in
advance for any pointers. Andy
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