How to change Read Only Constraint to Read-Write
 

Hi,

I am using singal of 32 bit's lenght in my .vhd file and I am
compiling using Makefile. I have also defined a UCF file. My UCF file
is generating error when run ngd build using Makefile. The error is
given below :

ERROR:
Reading component libraries for design expansion...

Annotating constraints to design from file "VIR3.ucf" ...
ERROR:NgdBuild:755 - Line 49 in 'VIR3.ucf': Could not find net(s)
'Input<7>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 50 in 'VIR3.ucf': Could not find net(s)
'Input<8>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 51 in 'VIR3.ucf': Could not find net(s)
'Input<9>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 52 in 'VIR3.ucf': Could not find net(s)
'Input<10>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 53 in 'VIR3.ucf': Could not find net(s)
'Input<11>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 54 in 'VIR3.ucf': Could not find net(s)
'Input<12>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 55 in 'VIR3.ucf': Could not find net(s)
'Input<13>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 56 in 'VIR3.ucf': Could not find net(s)
'Input<14>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 57 in 'VIR3.ucf': Could not find net(s)
'Input<15>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 58 in 'VIR3.ucf': Could not find net(s)
'Input<16>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 59 in 'VIR3.ucf': Could not find net(s)
'Input<17>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 60 in 'VIR3.ucf': Could not find net(s)
'Input<18>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 61 in 'VIR3.ucf': Could not find net(s)
'Input<19>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 62 in 'VIR3.ucf': Could not find net(s)
'Input<20>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 63 in 'VIR3.ucf': Could not find net(s)
'Input<21>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 64 in 'VIR3.ucf': Could not find net(s)
'Input<22>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 65 in 'VIR3.ucf': Could not find net(s)
'Input<23>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 66 in 'VIR3.ucf': Could not find net(s)
'Input<24>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 67 in 'VIR3.ucf': Could not find net(s)
'Input<25>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 68 in 'VIR3.ucf': Could not find net(s)
'Input<26>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 69 in 'VIR3.ucf': Could not find net(s)
'Input<27>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 70 in 'VIR3.ucf': Could not find net(s)
'Input<28>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 71 in 'VIR3.ucf': Could not find net(s)
'Input<29>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 72 in 'VIR3.ucf': Could not find net(s)
'Input<30>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:NgdBuild:755 - Line 73 in 'VIR3.ucf': Could not find net(s)
'Input<31>' in the design. To suppress this error use the -aul
switch,
specify the correct net name or remove the constraint.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file
"VIR3.ucf".


--------------------------------------------------------------------------------

I used -aul switch in my ngdbuild statement but this action simply
delete this message. And in the actual *.par file I could not see
signal's greater than 6th bits ( i.e there is no pin assignent of
Input greater than Input<6>.


Then, I comment all the signal Input<7> to Input <31> in my UCF file
and did NDG bulild. After doing this I could see pin assignment for
Input <0> to Input <6> as before.

After doing this I used ngd file and UCF file ( but this time all
signal's Input <0> to Input <31> were uncommented) . I used these both
file to see whats happening in Contraint Editor comes with Xilinx ISE
5.1
Keep one thing in mind that ngd file is produce using constraint
higher than 6 being commented and UCF file is used having all the
signal 0 to 31 uncommented .
I found that
1. In UCF Contraint (Read-Write) tab
NET "Input<0>" LOC = "P94" ;
NET "Input<1>" LOC = "P96" ;
NET "Input<2>" LOC = "P99" ;
NET "Input<3>" LOC = "P101" ;
NET "Input<4>" LOC = "P103" ;
NET "Input<5>" LOC = "P107" ;
NET "Input<6>" LOC = "P109" ;

2. In UCF Constraint ( Read Only) tab

NET "Input<7>" LOC = "P111" ;
NET "Input<8>" LOC = "P125" ;
NET "Input<9>" LOC = "P126" ;
NET "Input<10>" LOC = "P127" ;
NET "Input<11>" LOC = "P128" ;
NET "Input<12>" LOC = "P130" ;
NET "Input<13>" LOC = "P131" ;
NET "Input<14>" LOC = "P132" ;
NET "Input<15>" LOC = "P133" ;
NET "Input<16>" LOC = "P139" ;
NET "Input<17>" LOC = "P140" ;
NET "Input<18>" LOC = "P141" ;
NET "Input<19>" LOC = "P142" ;
NET "Input<20>" LOC = "P144" ;
NET "Input<21>" LOC = "P146" ;
NET "Input<22>" LOC = "P147" ;
NET "Input<23>" LOC = "P149" ;
NET "Input<24>" LOC = "P152" ;
NET "Input<25>" LOC = "P153" ;
NET "Input<26>" LOC = "P154" ;
NET "Input<27>" LOC = "P155" ;
NET "Input<28>" LOC = "P157" ;
NET "Input<29>" LOC = "P159" ;
NET "Input<30>" LOC = "P160" ;
NET "Input<31>" LOC = "P161" ;

Now, could any body tell what to do now in order to assigned pin's to
all the rest of the bit's


Any help would be appreciated

Rgds
Isaac

Re: How to change Read Only Constraint to Read-Write
 

On 9 Jul 2003 06:08:30 -0700, [email protected] (Isaac) wrote

>Hi,
>
>I am using singal of 32 bit's lenght in my .vhd file and I am
>compiling using Makefile. I have also defined a UCF file. My UCF file
>is generating error when run ngd build using Makefile. The error is
>given below :

Are you sure your signal is 32 bits? You might have declared it as 32
bits, but the synthesiser may remove bits (such as 31 downto 7) if
they are not used. This could cause the error messages you saw.

For an input port, "not used" means that (after logic reduction) it
doesn't affect any outputs.

Regards,
Allan.

Re: How to change Read Only Constraint to Read-Write
 

Yes ALLAN I am Sure I am using different bits


E.g

This VHDL code I tried but in PAR file no pin assignment for signal 13 to 7

process(CLK_2X,SR_ADDR_IO_int,SR_DATA_IO_int,SR_IR D_int,SR_IWR_int,SR_IVCS_V3_int)
begin
if RISING_EDGE(CLK_2X) then
if SR_IVCS_V3_int = '0' then
if SR_IWR_int = '0' then
if SR_ADDR_IO_int = "001100" then
LED_V3_int <= SR_DATA_IO_int(13 downto 7);
end if;
end if;
end if;
end if;
end process P_SRAM2LED;

Re: How to change Read Only Constraint to Read-Write
 

Sorry , I changes my code to Input .......
So please read SR_DATA_IO_int (13 downto 0) as Input (13 downto 0)

Cheers

Isaac


Allan Herriman <[email protected]> wrote in message news:<[email protected]>. ..
> On 9 Jul 2003 11:00:32 -0700, [email protected] (Isaac) wrote:
>
> >Yes ALLAN I am Sure I am using different bits
> >
> >
> >E.g
> >
> >This VHDL code I tried but in PAR file no pin assignment for signal 13 to 7
> >
> > process(CLK_2X,SR_ADDR_IO_int,SR_DATA_IO_int,SR_IR D_int,SR_IWR_int,SR_IVCS_V3_int)
> >begin
> > if RISING_EDGE(CLK_2X) then
> > if SR_IVCS_V3_int = '0' then
> > if SR_IWR_int = '0' then
> > if SR_ADDR_IO_int = "001100" then
> > LED_V3_int <= SR_DATA_IO_int(13 downto 7);
> > end if;
> > end if;
> > end if;
> > end if;
> >end process P_SRAM2LED;
>
>
> It's hard to say exactly what's going on, because you didn't include
> the right bits of VHDL (i.e. the signal declarations).
> Which signal is related to the "INPUT" signal in your first post?
>
> The only signal is likely to be of type std_logic_vector is
> SR_ADDR_IO_int, and that is only six bits long. Hmmm, the error
> messages indicated that the six least signficant bits of INPUT were
> used.
> Do you have an assignment like:
> SR_ADDR_IO_int <= INPUT(5 downto 0);
> anywhere in your code?
>
> You also might want to fix the sensitivity list.
>
> Regards,
> Allan.