FPGA Central

How can one synthesize their Verilog code into FPGA SLICEs without
doing PAR? I want the code to synthesize into SLICEs, not the
lower-level LUTs/MUXs/FFs (which is what a "Generate Post-Map
Simulation Model" in Xilinx ISE gives me). Ideally the output of the
synthesis would almost exclusively consist of SLICEs.

Thanks for your help,
Yannis

imavroid schrieb:
> How can one synthesize their Verilog code into FPGA SLICEs without
> doing PAR? I want the code to synthesize into SLICEs, not the
> lower-level LUTs/MUXs/FFs (which is what a "Generate Post-Map
> Simulation Model" in Xilinx ISE gives me). Ideally the output of the
> synthesis would almost exclusively consist of SLICEs.

Clustering these components into slices is already a partial placement.
It is controversial whether inital clustering helps or hurts placement.
(At least it helps the tool runtime)

IIRC the ISE synthesis tool has an option to pack LUTs to slices. If you
turn it on the information which LUTs belong to the same slice must be
in one of the files generated. You can than simply assign the muxes and
flip-flops to the same slices as the LUTs driving them and have a
netlist of Slices.

Kolja Sulimma

Thanks for your answer. The "Slice Packing" option in ISE's
Synthesize-XST properties is already set by default but that only makes
synthesis use the LUT#_L primitives. I couldn't find the LUT-Slice
association in any file.

In any case, I wish there was a way to generate the netlist of Slices
using already existing tools. Is there a "SLICE" primitive somewhere,
that could be used by synthesis tools? What I'm trying to do is
generate a "uniform" synthesis output (uniform in the sense that only
one module is almost exclusively used). I don't really care whether it
is Xilinx's Slices or some other FPGA vendor's or whatever. Just a
"uniform" netlist output from synthesis.

Any suggestions?

Yannis

imavroid schrieb:
> Thanks for your answer. The "Slice Packing" option in ISE's
> Synthesize-XST properties is already set by default but that only makes
> synthesis use the LUT#_L primitives. I couldn't find the LUT-Slice
> association in any file.
A LUT#_L can only connect to components in the same slice so the
clustering is implicit.
This way you get at least clusters of half slices. You might not get
information about how thes half slices are paired when the logic is
independant, but in that case placement should really handle the halfs
independantly anyway.

> In any case, I wish there was a way to generate the netlist of Slices
> using already existing tools. Is there a "SLICE" primitive somewhere,
> that could be used by synthesis tools? What I'm trying to do is
> generate a "uniform" synthesis output (uniform in the sense that only
> one module is almost exclusively used). I don't really care whether it
> is Xilinx's Slices or some other FPGA vendor's or whatever. Just a
> "uniform" netlist output from synthesis.
A slice has too many timing pathes and to many configuration options to
be a useful primitive for anything but placement. Therefore even if I
made the decision to use slices as my placement primitive (which might
not be a good choice) I would implement it as a cluster of lower level
primitives that describe timing and function. Therefore I doubt that you
find a tool that synthesizes to slices.

> Any suggestions?

Yes, there are acadamic tools that map to LUTs + DFFs.
See what University of Toronto has to offer.


Kolja Sulimma