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  #1 (permalink)  
Old 04-23-2006, 06:09 AM
Devlin
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Default How to avoid this waring in ISE 8.1?

When I complied any project with ISE 8.1 webpack with SP3, I got
warnings like below:

WARNING:ProjectMgmt - "G:/test/watchver/stopwatch_map.ngm" line 0
duplicate design unit: 'Module|stopwatch'
WARNING:ProjectMgmt - "G:/test/watchver/stopwatch.ngc" line 0 duplicate
design unit: 'Module|stopwatch'

Does anyone know what does it mean? or how can I avoid this?
thanks a lot.

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  #2 (permalink)  
Old 04-24-2006, 06:08 PM
Dave Pollum
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Default Re: How to avoid this waring in ISE 8.1?


Devlin wrote:
> When I complied any project with ISE 8.1 webpack with SP3, I got
> warnings like below:
>
> WARNING:ProjectMgmt - "G:/test/watchver/stopwatch_map.ngm" line 0
> duplicate design unit: 'Module|stopwatch'
> WARNING:ProjectMgmt - "G:/test/watchver/stopwatch.ngc" line 0 duplicate
> design unit: 'Module|stopwatch'
>
> Does anyone know what does it mean? or how can I avoid this?
> thanks a lot.


You're not alone. I get this warning, too. And I don't know what it
means or how to avoid it either!
-Dave Pollum

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  #3 (permalink)  
Old 04-24-2006, 07:21 PM
John_H
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Default Re: How to avoid this waring in ISE 8.1?

"Devlin" <[email protected]> wrote in message
news:[email protected] oups.com...
> When I complied any project with ISE 8.1 webpack with SP3, I got
> warnings like below:
>
> WARNING:ProjectMgmt - "G:/test/watchver/stopwatch_map.ngm" line 0
> duplicate design unit: 'Module|stopwatch'
> WARNING:ProjectMgmt - "G:/test/watchver/stopwatch.ngc" line 0 duplicate
> design unit: 'Module|stopwatch'
>
> Does anyone know what does it mean? or how can I avoid this?
> thanks a lot.


If you have an include file with a verilog module (stopwatch) then every
time you reference that include file it will see that a module of that name
has already been defined. It may be that an identical implementation will
give a warning while a different implementation will give an error or at
least a different warning. This all may also apply to VHDL.


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  #4 (permalink)  
Old 04-24-2006, 08:29 PM
Dave Pollum
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Default Re: How to avoid this waring in ISE 8.1?


John_H wrote:
> "Devlin" <[email protected]> wrote in message
> news:[email protected] oups.com...
> > When I complied any project with ISE 8.1 webpack with SP3, I got
> > warnings like below:
> >
> > WARNING:ProjectMgmt - "G:/test/watchver/stopwatch_map.ngm" line 0
> > duplicate design unit: 'Module|stopwatch'
> > WARNING:ProjectMgmt - "G:/test/watchver/stopwatch.ngc" line 0 duplicate
> > design unit: 'Module|stopwatch'
> >
> > Does anyone know what does it mean? or how can I avoid this?
> > thanks a lot.

>
> If you have an include file with a verilog module (stopwatch) then every
> time you reference that include file it will see that a module of that name
> has already been defined. It may be that an identical implementation will
> give a warning while a different implementation will give an error or at
> least a different warning. This all may also apply to VHDL.


John;
This is the warning message I get when running a VHDL project using ISE
8.1SP3: "..MON_v3.NGR line 0 duplicate design unit: Module|Mon_v3",
where "MON_v3" is my top VHDL module. I also have 2 lower level
modules. I built a very similar project with no errors/warnings when
I used ISE 7.1SP4.

I tried seaching for "duplicate design unit" on Xilinx's web site, but
didn't find the warning.
Would this be suitable for a web-case?
-Dave Pollum

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  #5 (permalink)  
Old 04-24-2006, 08:52 PM
John_H
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Default Re: How to avoid this waring in ISE 8.1?

"Dave Pollum" <[email protected]> wrote in message
news:[email protected] ups.com...
>
> John;
> This is the warning message I get when running a VHDL project using ISE
> 8.1SP3: "..MON_v3.NGR line 0 duplicate design unit: Module|Mon_v3",
> where "MON_v3" is my top VHDL module. I also have 2 lower level
> modules. I built a very similar project with no errors/warnings when
> I used ISE 7.1SP4.
>
> I tried seaching for "duplicate design unit" on Xilinx's web site, but
> didn't find the warning.
> Would this be suitable for a web-case?
> -Dave Pollum


I'd expect unexplained/undocumented errors and warnings would each warrant a
web case.
I haven't run VHDL through XST - I'm a Verilog guy in Synplicity tools.

Would it be safe to say you don't use include files (at least ones that
reference the modules)? If you don't use them, the "duplicate" arrangement
I envisioned wouldn't be an issue.


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  #6 (permalink)  
Old 04-25-2006, 06:33 AM
Zara
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Default Re: How to avoid this waring in ISE 8.1?

On Mon, 24 Apr 2006 19:52:37 GMT, "John_H" <[email protected]>
wrote:

>"Dave Pollum" <[email protected]> wrote in message
>news:[email protected] oups.com...
>>
>> John;
>> This is the warning message I get when running a VHDL project using ISE
>> 8.1SP3: "..MON_v3.NGR line 0 duplicate design unit: Module|Mon_v3",
>> where "MON_v3" is my top VHDL module. I also have 2 lower level
>> modules. I built a very similar project with no errors/warnings when
>> I used ISE 7.1SP4.
>>
>> I tried seaching for "duplicate design unit" on Xilinx's web site, but
>> didn't find the warning.
>> Would this be suitable for a web-case?
>> -Dave Pollum

>
>I'd expect unexplained/undocumented errors and warnings would each warrant a
>web case.
>I haven't run VHDL through XST - I'm a Verilog guy in Synplicity tools.
>
>Would it be safe to say you don't use include files (at least ones that
>reference the modules)? If you don't use them, the "duplicate" arrangement
>I envisioned wouldn't be an issue.
>



I have a nice test project that uses only one VHDL file with the
description of a dual ported RAM. It gives that warning too. In fact
*every* VHDL project I have gives that warning.

Best regards,

Zara

PS: I never gave it more than five seconds thought, because I am more
worried by the hundreds of unavoidable warnings given by a project
containing an XPS/microblaze module.
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