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-   -   How to apply timing constrains for large bus (http://www.fpgacentral.com/group/showthread.php?t=58354)

vssumesh 04-17-2006 10:58 AM

How to apply timing constrains for large bus
 
Hi all,
I am working on a model which is basically a four bit 50 to 1
mux. There is four such blocks. To save area i am trying to time
multiplex the muxing that is only twi such blocks are created and the
data is latched with high and low levels of the clock. But the delay in
the mux block is such a large value which prevents the time
multiplexing of the signal. Applied "From to " constrain to the input
and output signals of the mux block but the PAR tool reported it as
ignored. It displplayed N/A at the requested and available time for
that group. Why it is like that.
In the timing analyser tool when a request is placed to measure
the delay between the input and output groups is placed it gave no
result. But when the delaye between invidual elements where requested
it gave result. is it necessary to specify timing constrain for each
element.
Is there any other methods by which we can reduce the muxing time.
The inputs of the mux blocks comes from FFs and the output goes to
latch which is controlled by high and low time of clock.
From the timing report it is found that the fanout for the
selection pins of the decoder is very high (50). And this gives the max
delay. Is there any way to tell the synthesizer to insert buffer to
reduce this high fanout. For the mux i am using indexing method like
out = in[sel];
I am stuck with this problem. Also i have little experiance with
the timng analysis. Please help me on this issue. I am working with
Virtex 2 and Xilinx ISE 7.1.
Thanks and regards
Sumesh V S


vssumesh 04-17-2006 03:25 PM

Re: How to apply timing constrains for large bus
 
One more doubt....
Tried to decrease the fanou by introducing bufferes for the
selection pins to the Mux. But it is not in the final output The Map is
optimizing the buffers away. It is listed in the xilinx library guide
also. But then how can we reduce the fanout or introduce extra
buffering....


John_H 04-17-2006 03:43 PM

Re: How to apply timing constrains for large bus
 
vssumesh wrote:
> One more doubt....
> Tried to decrease the fanou by introducing bufferes for the
> selection pins to the Mux. But it is not in the final output The Map is
> optimizing the buffers away. It is listed in the xilinx library guide
> also. But then how can we reduce the fanout or introduce extra
> buffering....


If the fanout of the select is your biggest problem, don't "buffer"
those signals but replicate the registers. You need to talk the
synthesizer into leaving the replicated logic in your design; in
SynplifyPro I'd use the syn_preserve directive to keep those replicated
registers in my design.

If you can pipeline your 50:1 mux you can keep the performance and the
simple mux structure rather than time-multiplexing a multiplex which...
shouldn't produce any net benefit.

vssumesh 04-18-2006 03:57 AM

Re: How to apply timing constrains for large bus
 
> If the fanout of the select is your biggest problem, don't "buffer"
> those signals but replicate the registers. You need to talk the
> synthesizer into leaving the replicated logic in your design; in
> SynplifyPro I'd use the syn_preserve directive to keep those replicated
> registers in my design.

So what you are suggesting is duplicate the registers in the code
and tell the synthesizer not to optimize it. Is there any way we can
force the synthesizer to do both.

> If you can pipeline your 50:1 mux you can keep the performance and the
> simple mux structure rather than time-multiplexing a multiplex which...
> shouldn't produce any net benefit.

This is not possible as i am not allowed to introduce any pipeline
stages.



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