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  #1 (permalink)  
Old 11-25-2007, 11:58 PM
Ben Jackson
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Default Hook open drain "power good" to nSTATUS or nCONFIG?

I'm using a Cyclone II with 1.2V core. The 1.2V regulator has an open
drain "power good" signal and a cap to delay that after startup.

It looks like I could hook this to either nSTATUS or nCONFIG to delay
FPGA configuration. The only difference I can see is that nSTATUS is
meant for daisy chaining FPGAs and does not appear to be tested after
configuration unless nCONFIG is first pulled low.

Looking at the Configuration Cycle State Machine (p1-5, figure 1-2 in
the configuration handbook) it looks like the chip itself has a
'power supply not stable' test, and it may not be necessary to hook up
PWRGD at all.

What's the best practice here?

--
Ben Jackson AD7GD
<[email protected]>
http://www.ben.com/
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  #2 (permalink)  
Old 11-26-2007, 12:33 PM
Allan Herriman
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Default Re: Hook open drain "power good" to nSTATUS or nCONFIG?

On Sun, 25 Nov 2007 17:58:24 -0600, Ben Jackson <[email protected]> wrote:

>I'm using a Cyclone II with 1.2V core. The 1.2V regulator has an open
>drain "power good" signal and a cap to delay that after startup.
>
>It looks like I could hook this to either nSTATUS or nCONFIG to delay
>FPGA configuration. The only difference I can see is that nSTATUS is
>meant for daisy chaining FPGAs and does not appear to be tested after
>configuration unless nCONFIG is first pulled low.
>
>Looking at the Configuration Cycle State Machine (p1-5, figure 1-2 in
>the configuration handbook) it looks like the chip itself has a
>'power supply not stable' test, and it may not be necessary to hook up
>PWRGD at all.
>
>What's the best practice here?



Connect PWRGD to nConfig. Do not let nConfig go high until all
supplies are within tolerance. (IOW, pull nConfig low if any supply
is out of tolerance.)


From the StratixIIGX data sheet:

"(4) VCCPD must ramp-up from 0 V to 3.3 V within 100 us to 100 ms. If
VCCPD is not ramped up within this specified
time, the Stratix II GX device will not configure successfully. If the
system does not allow for a VCCPD ramp-up time
of 100 ms or less, hold nCONFIG low until all power supplies are
reliable."


Since in general you will not be able to control brownouts (i.e. you
cannot guarantee any particular risetime), you really do need a
precision supply monitor.


Regards,
Allan
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  #3 (permalink)  
Old 11-26-2007, 12:57 PM
Allan Herriman
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Posts: n/a
Default Re: Hook open drain "power good" to nSTATUS or nCONFIG?

On Mon, 26 Nov 2007 23:33:44 +1100, Allan Herriman
<[email protected]> wrote:

>On Sun, 25 Nov 2007 17:58:24 -0600, Ben Jackson <[email protected]> wrote:
>
>>I'm using a Cyclone II with 1.2V core. The 1.2V regulator has an open
>>drain "power good" signal and a cap to delay that after startup.
>>
>>It looks like I could hook this to either nSTATUS or nCONFIG to delay
>>FPGA configuration. The only difference I can see is that nSTATUS is
>>meant for daisy chaining FPGAs and does not appear to be tested after
>>configuration unless nCONFIG is first pulled low.
>>
>>Looking at the Configuration Cycle State Machine (p1-5, figure 1-2 in
>>the configuration handbook) it looks like the chip itself has a
>>'power supply not stable' test, and it may not be necessary to hook up
>>PWRGD at all.
>>
>>What's the best practice here?

>
>
>Connect PWRGD to nConfig. Do not let nConfig go high until all
>supplies are within tolerance. (IOW, pull nConfig low if any supply
>is out of tolerance.)
>
>
>From the StratixIIGX data sheet:
>
>"(4) VCCPD must ramp-up from 0 V to 3.3 V within 100 us to 100 ms. If
>VCCPD is not ramped up within this specified
>time, the Stratix II GX device will not configure successfully. If the
>system does not allow for a VCCPD ramp-up time
>of 100 ms or less, hold nCONFIG low until all power supplies are
>reliable."
>
>
>Since in general you will not be able to control brownouts (i.e. you
>cannot guarantee any particular risetime), you really do need a
>precision supply monitor.



Somehow I managed to edit out the part where I explained that brownout
detectors made on linear chips (e.g. your regulator) are probably much
more accurate than the ones made on digital chips (e.g. your FPGA).
They also won't suffer from risetime limitations, etc.

Regards,
Allan
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  #4 (permalink)  
Old 11-26-2007, 01:07 PM
Allan Herriman
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Posts: n/a
Default Re: Hook open drain "power good" to nSTATUS or nCONFIG?

On Mon, 26 Nov 2007 23:57:04 +1100, Allan Herriman
<[email protected]> wrote:

>On Mon, 26 Nov 2007 23:33:44 +1100, Allan Herriman
><[email protected]> wrote:
>
>>On Sun, 25 Nov 2007 17:58:24 -0600, Ben Jackson <[email protected]> wrote:
>>
>>>I'm using a Cyclone II with 1.2V core. The 1.2V regulator has an open
>>>drain "power good" signal and a cap to delay that after startup.
>>>
>>>It looks like I could hook this to either nSTATUS or nCONFIG to delay
>>>FPGA configuration. The only difference I can see is that nSTATUS is
>>>meant for daisy chaining FPGAs and does not appear to be tested after
>>>configuration unless nCONFIG is first pulled low.
>>>
>>>Looking at the Configuration Cycle State Machine (p1-5, figure 1-2 in
>>>the configuration handbook) it looks like the chip itself has a
>>>'power supply not stable' test, and it may not be necessary to hook up
>>>PWRGD at all.
>>>
>>>What's the best practice here?

>>
>>
>>Connect PWRGD to nConfig. Do not let nConfig go high until all
>>supplies are within tolerance. (IOW, pull nConfig low if any supply
>>is out of tolerance.)
>>
>>
>>From the StratixIIGX data sheet:
>>
>>"(4) VCCPD must ramp-up from 0 V to 3.3 V within 100 us to 100 ms. If
>>VCCPD is not ramped up within this specified
>>time, the Stratix II GX device will not configure successfully. If the
>>system does not allow for a VCCPD ramp-up time
>>of 100 ms or less, hold nCONFIG low until all power supplies are
>>reliable."
>>
>>
>>Since in general you will not be able to control brownouts (i.e. you
>>cannot guarantee any particular risetime), you really do need a
>>precision supply monitor.

>
>
>Somehow I managed to edit out the part where I explained that brownout
>detectors made on linear chips (e.g. your regulator) are probably much
>more accurate than the ones made on digital chips (e.g. your FPGA).
>They also won't suffer from risetime limitations, etc.


Another note from the StratixIIGX data sheet:

"(3) Maximum VCC rise time is 100 ms, and VCC must rise monotonically
from ground to VCC."

To me, this implies that you need a precision (i.e. external) monitor
on all rails.
The last time I designed a board with an FPGA (last month), I used the
PWRGD outputs on several different regulators in conjunction with an
LTC2900 so that every rail on the board was monitored. The resultant
(active low) signal was ANDed into the nCONFIG signal.

The LTC2900 is expensive (~$3.63 Digikey), but flexible. There are
hundreds of similar parts to choose from.

Regards,
Allan
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  #5 (permalink)  
Old 11-26-2007, 02:59 PM
Eli Bendersky
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Posts: n/a
Default Re: Hook open drain "power good" to nSTATUS or nCONFIG?

On Nov 26, 1:58 am, Ben Jackson <[email protected]> wrote:
> I'm using a Cyclone II with 1.2V core. The 1.2V regulator has an open
> drain "power good" signal and a cap to delay that after startup.
>
> It looks like I could hook this to either nSTATUS or nCONFIG to delay
> FPGA configuration. The only difference I can see is that nSTATUS is
> meant for daisy chaining FPGAs and does not appear to be tested after
> configuration unless nCONFIG is first pulled low.
>
> Looking at the Configuration Cycle State Machine (p1-5, figure 1-2 in
> the configuration handbook) it looks like the chip itself has a
> 'power supply not stable' test, and it may not be necessary to hook up
> PWRGD at all.
>
> What's the best practice here?


I think it is best to use a voltage supervisor circuit that accurately
monitors Vcc and provides a clean and long reset signal. It's also
useful for brown-out conditions and orderly reset when the power
fails.

Eli
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