FPGA Central

Hello everybody, I'm interested in the implementation of a 32x32 bit
multiplier (unsigned values). The target FPGA is Virtex V300e
I would like to implement a system that is not too big, while I have
not a lot of timing constraints. Using a behavioral approach I obtain a
multiplier that needs about 17% of the FPGA, I would like to reduce
this size and the target frequency is about 70Mhz.
Where can I find some good manual that can help me in this task? can
you give me some advice about how to code this device?
Any help will be appreciated.

On 22 Sep 2005 08:18:54 -0700, "Giox" <[email protected]>
wrote:

>Hello everybody, I'm interested in the implementation of a 32x32 bit
>multiplier (unsigned values). The target FPGA is Virtex V300e
>I would like to implement a system that is not too big, while I have
>not a lot of timing constraints. Using a behavioral approach I obtain a
>multiplier that needs about 17% of the FPGA, I would like to reduce
>this size and the target frequency is about 70Mhz.
>Where can I find some good manual that can help me in this task? can
>you give me some advice about how to code this device?
>Any help will be appreciated.

Suppose you want to calculate p * q.
If p = a * 2^16 + b and q = c * 2^16 + d then
p * q = (a*c * 2^32 + (a*d+b*c) * 2^16 + b * d) which says that you
can use 4 16 bit multipliers to do a 32 bit multiplication or use one
16 bit multiplier and run it over 4 cycles to get what you want.

mk wrote:
> On 22 Sep 2005 08:18:54 -0700, "Giox" <[email protected]>
> wrote:
>
>
>>Hello everybody, I'm interested in the implementation of a 32x32 bit
>>multiplier (unsigned values). The target FPGA is Virtex V300e
>>I would like to implement a system that is not too big, while I have
>>not a lot of timing constraints. Using a behavioral approach I obtain a
>>multiplier that needs about 17% of the FPGA, I would like to reduce
>>this size and the target frequency is about 70Mhz.
>>Where can I find some good manual that can help me in this task? can
>>you give me some advice about how to code this device?
>>Any help will be appreciated.
>
>
> Suppose you want to calculate p * q.
> If p = a * 2^16 + b and q = c * 2^16 + d then
> p * q = (a*c * 2^32 + (a*d+b*c) * 2^16 + b * d) which says that you
> can use 4 16 bit multipliers to do a 32 bit multiplication or use one
> 16 bit multiplier and run it over 4 cycles to get what you want.
>

Using karatsuba, you might get away with only 3 multipliers and just a
few extralogic.


Sylvain

Giox wrote:

>Hello everybody, I'm interested in the implementation of a 32x32 bit
>multiplier (unsigned values). The target FPGA is Virtex V300e
>I would like to implement a system that is not too big, while I have
>not a lot of timing constraints. Using a behavioral approach I obtain a
>multiplier that needs about 17% of the FPGA, I would like to reduce
>this size and the target frequency is about 70Mhz.
>Where can I find some good manual that can help me in this task? can
>you give me some advice about how to code this device?
>Any help will be appreciated.
>
>
>
Do you need a result on every cycle of the 70 MHz clock? If not, then
you can do the multiplication over several clock cycles summing the
partial products in an accumulator. Look at the multipliers page on my
website (Under the DSP section) for some guidance on different multipliers.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email [email protected]
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

Thanks a lot, I will read it.
Thanks to everyone
Gio