Hidden debug print in ISE ( XIL_PROJNAV_FLOW_DEBUG_LEVEL)
Perhaps this can help someone. I've spent a day trying to understand why
suddenly I couldn't build an archived ISE/EDK 8.2 project anymore. The ISE
would just stop for no reason producing no reports. I still don't know why
this happened, but at least I found how to work around the problem. I found
in the Xilinx knowledge base that there is an environment variable
XIL_PROJNAV_FLOW_DEBUG_LEVEL one can set to 99 to enable debug prints. I did
it and it actually pointed me to a problem with attaching two IP cores to
the design. There is still no explanation of why it worked before, but as I
said at least I was able to work around the issue.
/Mikhail
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