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  #1 (permalink)  
Old 07-06-2008, 11:11 AM
Zhane
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Posts: n/a
Default Help to SImulate Uart TX

I'm using the following code. I've managed to make it work on my fpga
before. but when I try to simulate on my modelsim, it seems that it
never gets into the statemachine.

I've configured the settings for a 50Mhz clock...also set the config
for model sim to be 10ns 10ns for clock high and low.

How should I go about simulating this?



------------------------------------------------------------------------------
--
-- Engineer: Wojciech Powiertowski
--
-- Module Name: transmitter
-- Project Name: UART
-- Description: A VHDL UART controller
--
-- Comments:
-- If your clkFreq or baudRate values are different than you should
-- calculate proper: phase accumulator width and proper tuning word
with
-- the following equations:
-- phaseAccWidth = round(log2((clkFreq/(baudRate))^2))
-- phaseAccTuning = round(baudRate*2^(phaseAccWidth+1)/clkFreq)
--
-- Example:
-- clkFreq = 100000000 -- 100MHz
-- baudRate = 115200 -- 115.2kHz
-- phaseAccWidth = 19.5233 -- round it up to 20
-- phaseAccTuning = 2415.9 -- round it up to 2416
--
-- generated baud will have frequency of 115199.99 which is only
-- 0.000005% different than ideal baud rate of 115200
--
------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity transmitter is
port(
clk : in std_logic;
startTxD : in std_logic;
reset : in std_logic;
dataTxD : in std_logic_vector (7 downto 0);
TxD : out std_logic;
showtick : out std_logic;
busyTxD : out std_logic
);
end transmitter;

architecture TxD_arch of transmitter is
-- phase accumulator constants and core - see details on top of the
file !!!
constant phaseAccWidth : integer := 25;
constant phaseAccTuning : integer := 12885;
signal phaseAcc : std_logic_vector (phaseAccWidth downto 0);

-- signals in design
signal dataBuffer : std_logic_vector (7 downto 0);
signal baudTick : std_logic;
signal state : integer range 0 to 15;
begin

-- baud generator based on phase accumulator
baudTickGen : process (clk) is begin
if(rising_edge(clk))then
phaseAcc <= phaseAcc + phaseAccTuning;
end if;
end process baudTickGen;
-- MSB of phase accumulator generates the proper baud rate
baudTick <= phaseAcc(phaseAccWidth);


-- transmitter: 8 bits of data, no parity control, 1 stop bit
transmitter : process (baudTick) is begin


if(rising_edge(baudTick))then
showtick <='1';
if(reset = '1')then
state <= 0;
dataBuffer <= (others => '0');
else
if(state = 0 and startTxD = '0')then
busyTxD <= '0';
TxD <= '1';
elsif(state = 0 and startTxD = '1')then
TxD <= '0';
dataBuffer <= dataTxD;
busyTxD <= '1';
state <= state + 1;
elsif(state > 0 and state < 9)then
busyTxD <= '1';
TxD <= dataBuffer(state-1);
state <= state + 1;
elsif(state = 9)then
TxD <= '1';
busyTxD <= '1';
state <= 0;
end if;
end if;


end if;
end process;

end TxD_arch;
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  #2 (permalink)  
Old 07-06-2008, 05:44 PM
KJ
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Posts: n/a
Default Re: Help to SImulate Uart TX


"Zhane" <[email protected]> wrote in message
news:[email protected]m...
> I'm using the following code. I've managed to make it work on my fpga
> before. but when I try to simulate on my modelsim, it seems that it
> never gets into the statemachine.
>


'Never gets into the statemachine'....is that supposed to mean something?
(Hint: It doesn't)

> I've configured the settings for a 50Mhz clock...also set the config
> for model sim to be 10ns 10ns for clock high and low.
>
> How should I go about simulating this?
>


In a word, 'debug'.

Put some waveforms up to view, step through the code, look at the signals,
however it is that works best for you. It's your design and testbench, it's
up to you to figure out what the problem is. Debugging by newsgroup is
hardly worth the effort.

KJ


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  #3 (permalink)  
Old 07-06-2008, 06:30 PM
Mike Treseler
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Posts: n/a
Default Re: Help to SImulate Uart TX

Zhane wrote:
> I'm using the following code. I've managed to make it work on my fpga
> before. but when I try to simulate on my modelsim, it seems that it
> never gets into the statemachine.


Maybe rising_edge(baudTick) isn't happening.
Have a look at that wave.
A better design would use clk here
and make baudTick a clock enable.

> I've configured the settings for a 50Mhz clock...also set the config
> for model sim to be 10ns 10ns for clock high and low.


What settings?
I would write my own sim clock process.

> How should I go about simulating this?


I would buy a quartus license to get their oem modelsim.

-- Mike Treseler

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  #4 (permalink)  
Old 07-07-2008, 02:58 AM
Zhane
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Posts: n/a
Default Re: Help to SImulate Uart TX

On Jul 6, 11:44*pm, "KJ" <[email protected]> wrote:
> "Zhane" <[email protected]> wrote in message
>
> news:[email protected]m...
>
> > I'm using the following code. I've managed to make it work on my fpga
> > before. but when I try to simulate on my modelsim, it seems that it
> > never gets into the statemachine.

>
> 'Never gets into the statemachine'....is that supposed to mean something?
> (Hint: *It doesn't)
>
> > I've configured the settings for a 50Mhz clock...also set the config
> > for model sim to be 10ns 10ns for clock high and low.

>
> > How should I go about simulating this?

>
> In a word, 'debug'.
>
> Put some waveforms up to view, step through the code, look at the signals,
> however it is that works best for you. *It's your design and testbench,it's
> up to you to figure out what the problem is. *Debugging by newsgroup is
> hardly worth the effort.
>
> KJ


I did
the baudtick does changes, but it doesnt get into the

if(rising_edge(baudTick))then
showtick <='1';

section. I've no idea why it happens though..since baudtick changes..
there should be a rising edge
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  #5 (permalink)  
Old 07-07-2008, 03:07 AM
Zhane
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Posts: n/a
Default Re: Help to SImulate Uart TX

On Jul 7, 12:30*am, Mike Treseler <[email protected]> wrote:
> Zhane wrote:
> > I'm using the following code. I've managed to make it work on my fpga
> > before. but when I try to simulate on my modelsim, it seems that it
> > never gets into the statemachine.

>
> Maybe rising_edge(baudTick) isn't happening.
> Have a look at that wave.
> A better design would use clk here
> and make baudTick a clock enable.
>
> > I've configured the settings for a 50Mhz clock...also set the config
> > for model sim to be 10ns 10ns for clock high and low.

>
> What settings?
> I would write my own sim clock process.
>
> > How should I go about simulating this?

>
> I would buy a quartus license to get their oem modelsim.
>
> * * * * * -- Mike Treseler


I changed the settings of the baudgen to match my 9600bps and my 50Mhz
clock.

I'm noob, so trying to save some effort from recoding by using this
code which I found somewhere ~_~

it did work when I try on the actual fpga...
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  #6 (permalink)  
Old 07-07-2008, 03:31 AM
Mike Treseler
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Posts: n/a
Default Re: Help to SImulate Uart TX

Zhane wrote:

> I've no idea why it happens though..since baudtick changes..
> there should be a rising edge


Does the testbench wait for 2*12885 clk cycles per 'tick'
Does the testbench drive reset back low?
Good luck.

-- Mike Treseler

PS:
Might want to reset showtick.
Might want to strobify the MSB and sync up both counters to clk.
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  #7 (permalink)  
Old 07-07-2008, 05:24 AM
Zhane
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Posts: n/a
Default Re: Help to SImulate Uart TX

On Jul 7, 9:31*am, Mike Treseler <[email protected]> wrote:
> Zhane wrote:
> > I've no idea why it happens though..since baudtick changes..
> > there should be a rising edge

>
> Does the testbench wait for 2*12885 clk cycles per 'tick'
> Does the testbench drive reset back low?
> Good luck.
>
> * -- Mike Treseler
>
> PS:
> Might want to reset showtick.
> Might want to strobify the MSB and sync up both counters to clk.


hmm
sorry ... i dont understand what you mean by ..
> Does the testbench wait for 2*12885 clk cycles per 'tick'
> Might want to strobify the MSB and sync up both counters to clk.


=_=!!
i only put my reset up for 1 cycle only..the remaining are all low
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  #8 (permalink)  
Old 07-08-2008, 12:46 AM
Mike Treseler
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Posts: n/a
Default Re: Help to SImulate Uart TX

Zhane wrote:

> I'm noob, so trying to save some effort from recoding by using this
> code which I found somewhere ~_~


If you want to understand it well enough to test it,
read up on direct digital synthesis.

> it did work when I try on the actual fpga...


Good luck.

-- Mike Treseler
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  #9 (permalink)  
Old 07-22-2008, 12:28 PM
wojtek
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Posts: n/a
Default Re: Help to SImulate Uart TX

On 8 Lip, 00:46, Mike Treseler <[email protected]> wrote:
> Zhane wrote:
> > I'm noob, so trying to save some effort from recoding by using this
> > code which I found somewhere ~_~

>
> If you want to understand it well enough to test it,
> read up on direct digital synthesis.
>
> > it did work when I try on the actual fpga...

>
> Good luck.
>
> -- Mike Treseler


Let me give some suggestions (since I am the author of the code), for
simulation purposes put somewhere
baudTick <= clk;
and omit the phase accumulator

Good luck, oh and if you have any other questions simply write an e-
mail or something since I don't usually check discussion groups.
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  #10 (permalink)  
Old 07-22-2008, 12:32 PM
wojtek
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Posts: n/a
Default Re: Help to SImulate Uart TX

>A better design would use clk here
>and make baudTick a clock enable.


@ Mike: I'm afraid it wouldn't work, I'm not sure if you get how the
phase accumulator works, trust me it is ok the way it is.



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  #11 (permalink)  
Old 07-22-2008, 01:03 PM
Newman
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Posts: n/a
Default Re: Help to SImulate Uart TX

On Jul 22, 6:32*am, wojtek <[email protected]> wrote:
> >A better design would use clk here
> >and make baudTick a clock enable.

>
> @ Mike: I'm afraid it wouldn't work, I'm not sure if you get how the
> phase accumulator works, trust me it is ok the way it is.


I suspect Mike knows how a phase accumulator works. The rising edge
of the phase accumulator can be detected without having it be a clock
input. Some people cringe when they see a register output used as an
input clock to other synchronous logic and will go to great lengths to
avoid it because they might have to explain why this will never cause
a timing issue. In general, I would not easily discount what Mike has
to say IMHO.
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  #12 (permalink)  
Old 07-22-2008, 01:29 PM
wojtek
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Posts: n/a
Default Re: Help to SImulate Uart TX

On 22 Lip, 13:03, Newman <[email protected]> wrote:
> On Jul 22, 6:32 am, wojtek <[email protected]> wrote:
>
> > >A better design would use clk here
> > >and make baudTick a clock enable.

>
> > @ Mike: I'm afraid it wouldn't work, I'm not sure if you get how the
> > phase accumulator works, trust me it is ok the way it is.

>
> I suspect Mike knows how a phase accumulator works. The rising edge
> of the phase accumulator can be detected without having it be a clock
> input. Some people cringe when they see a register output used as an
> input clock to other synchronous logic and will go to great lengths to
> avoid it because they might have to explain why this will never cause
> a timing issue. In general, I would not easily discount what Mike has
> to say IMHO.


You got me wrong, I don't discount Mike's suggestions (I am very sorry
Mike if you get the impression). Just in this case, the aim of phase
accumulator is to create a clock, and using MSB of phaseAcc as clock
enable would cause the UART to work with clk frequency not with the
baudTick frequency. Since most DCM's aren't able to create a frequency
of less than 10MHz, using phase accumulator to do it is pretty good
idea (and it will be quite precise as well).
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  #13 (permalink)  
Old 07-22-2008, 03:43 PM
Mike Treseler
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Posts: n/a
Default Re: Help to SImulate Uart TX

mike wrote:
>>>> A better design would use clk here
>>>> and make baudTick a clock enable.


wojtek wrote:
>>> @ Mike: I'm afraid it wouldn't work, I'm not sure if you get how the
>>> phase accumulator works, trust me it is ok the way it is.


I get the phase accumulator,
but why bother with the fussy DCM at all?

Newman wrote:
>> Some people cringe when they see a register output used as an
>> input clock to other synchronous logic and will go to great lengths to
>> avoid it because they might have to explain why this will never cause
>> a timing issue.


I avoid it because
I prefer writing code
to writing clock domain constraints.

> Since most DCM's aren't able to create a frequency
> of less than 10MHz, using phase accumulator to do it is pretty good
> idea (and it will be quite precise as well).


I agree.
So why did you punt it?
A phase accumulator is portable, flexible and a precise as I need.
See also:
http://groups.google.com/groups/search?q=accum_s

-- Mike Treseler
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  #14 (permalink)  
Old 07-22-2008, 05:00 PM
Newman
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Posts: n/a
Default Re: Help to SImulate Uart TX

On Jul 22, 9:43*am, Mike Treseler <[email protected]> wrote:
> mike wrote:
> >>>> A better design would use clk here
> >>>> and make baudTick a clock enable.

> wojtek wrote:
> >>> @ Mike: I'm afraid it wouldn't work, I'm not sure if you get how the
> >>> phase accumulator works, trust me it is ok the way it is.

>
> I get the phase accumulator,
> but why bother with the fussy DCM at all?
>
> Newman wrote:
> >> Some people cringe when they see a register output used as an
> >> input clock to other synchronous logic and will go to great lengths to
> >> avoid it because they might have to explain why this will never cause
> >> a timing issue. *

>
> I avoid it because
> I prefer writing code
> to writing clock domain constraints.
>
> > Since most DCM's aren't able to create a frequency
> > of less than 10MHz, using phase accumulator to do it is pretty good
> > idea (and it will be quite precise as well).

>
> I agree.
> So why did you punt it?
> A phase accumulator is portable, flexible and a precise as I need.
> See also:http://groups.google.com/groups/search?q=accum_s
>
> * * * * -- Mike Treseler



Hi Wojtek

I noted with "-- Look Here ZZZ" comments where preliminary changes
could be
investigated to eliminate a clock domain. baudTick becomes a
synchronously delayed
version of phaseAcc(phaseAccWidth) and can be used to detect the
rising edge of
phaseAcc(phaseAccWidth) after a clock cycle delay. I did not
simulate it or anything.

-- baud generator based on phase accumulator
baudTickGen : process (clk) is begin
if(rising_edge(clk))then
phaseAcc <= phaseAcc + phaseAccTuning;
baudTick <= phaseAcc(phaseAccWidth); -- Look Here ZZZ
end if;
end process baudTickGen;
-- MSB of phase accumulator generates the proper baud rate
-- Look Here ZZZ baudTick <= phaseAcc(phaseAccWidth);


-- transmitter: 8 bits of data, no parity control, 1 stop bit
-- Look Here ZZZ transmitter : process (baudTick) is begin
transmitter : process (clk) is begin -- Look Here


-- Look HereZZZ if(rising_edge(baudTick))then
if((baudTick = '0') and (phaseAcc(phaseAccWidth) = '1')) then --
Look Here ZZZ
showtick <='1';
if(reset = '1')then
state <= 0;
dataBuffer <= (others => '0');
else
if(state = 0 and startTxD = '0')then
busyTxD <= '0';
TxD <= '1';
elsif(state = 0 and startTxD = '1')then
TxD <= '0';
dataBuffer <= dataTxD;
busyTxD <= '1';
state <= state + 1;
elsif(state > 0 and state < 9)then
busyTxD <= '1';
TxD <= dataBuffer(state-1);
state <= state + 1;
elsif(state = 9)then
TxD <= '1';
busyTxD <= '1';
state <= 0;
end if;
end if;


end if;
end process;


end TxD_arch;


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  #15 (permalink)  
Old 07-22-2008, 05:20 PM
Newman
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Posts: n/a
Default Re: Help to SImulate Uart TX

On Jul 22, 11:00*am, Newman <[email protected]> wrote:
> On Jul 22, 9:43*am, Mike Treseler <[email protected]> wrote:
>
>
>
>
>
> > mike wrote:
> > >>>> A better design would use clk here
> > >>>> and make baudTick a clock enable.

> > wojtek wrote:
> > >>> @ Mike: I'm afraid it wouldn't work, I'm not sure if you get how the
> > >>> phase accumulator works, trust me it is ok the way it is.

>
> > I get the phase accumulator,
> > but why bother with the fussy DCM at all?

>
> > Newman wrote:
> > >> Some people cringe when they see a register output used as an
> > >> input clock to other synchronous logic and will go to great lengths to
> > >> avoid it because they might have to explain why this will never cause
> > >> a timing issue. *

>
> > I avoid it because
> > I prefer writing code
> > to writing clock domain constraints.

>
> > > Since most DCM's aren't able to create a frequency
> > > of less than 10MHz, using phase accumulator to do it is pretty good
> > > idea (and it will be quite precise as well).

>
> > I agree.
> > So why did you punt it?
> > A phase accumulator is portable, flexible and a precise as I need.
> > See also:http://groups.google.com/groups/search?q=accum_s

>
> > * * * * -- Mike Treseler

>
> Hi Wojtek
>
> * I noted with "-- Look Here ZZZ" comments where preliminary changes
> could be
> investigated to eliminate a clock domain. *baudTick becomes a
> synchronously delayed
> version of phaseAcc(phaseAccWidth) and can be used to detect the
> rising edge of
> phaseAcc(phaseAccWidth) after a *clock cycle delay. *I did not
> simulate it or anything.
>
> -- baud generator based on phase accumulator
> * baudTickGen : process (clk) is begin
> * * if(rising_edge(clk))then
> * * * phaseAcc <= phaseAcc + phaseAccTuning;
> * * * baudTick <= phaseAcc(phaseAccWidth); * * * *-- LookHere ZZZ
> * * end if;
> * end process baudTickGen;
> * -- MSB of phase accumulator generates the proper baud rate
> * -- Look Here ZZZ baudTick <= phaseAcc(phaseAccWidth);
>
> * -- transmitter: 8 bits of data, no parity control, 1 stop bit
> * -- Look Here ZZZ transmitter : process (baudTick) is begin
> * transmitter : process (clk) is begin *-- Look Here
>
> * * -- Look HereZZZ *if(rising_edge(baudTick))then
> * * if((baudTick = '0') and (phaseAcc(phaseAccWidth) = '1')) then* --
> Look Here ZZZ
> * * * * showtick <='1';
> * * * if(reset = '1')then
> * * * * state <= 0;
> * * * * dataBuffer <= (others => '0');
> * * * else
> * * * * if(state = 0 and startTxD = '0')then
> * * * * * busyTxD <= '0';
> * * * * * TxD <= '1';
> * * * * elsif(state = 0 and startTxD = '1')then
> * * * * * TxD <= '0';
> * * * * * dataBuffer <= dataTxD;
> * * * * * busyTxD <= '1';
> * * * * * state <= state + 1;
> * * * * elsif(state > 0 and state < 9)then
> * * * * * busyTxD <= '1';
> * * * * * TxD <= dataBuffer(state-1);
> * * * * * state <= state + 1;
> * * * * elsif(state = 9)then
> * * * * * TxD <= '1';
> * * * * * busyTxD <= '1';
> * * * * * state <= 0;
> * * * * end if;
> * * * end if;
>
> * * * * *end if;
> * end process;
>
> end TxD_arch;- Hide quoted text -
>
> - Show quoted text -



-- forgot if(rising_edge(clk))then stuff in transmitter process
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  #16 (permalink)  
Old 07-23-2008, 01:23 AM
Guest
 
Posts: n/a
Default Re: Help to SImulate Uart TX

On 22 Jul., 17:00, Newman <[email protected]> wrote:
> On Jul 22, 9:43 am, Mike Treseler <[email protected]> wrote:
>
>
>
> > mike wrote:
> > >>>> A better design would use clk here
> > >>>> and make baudTick a clock enable.

> > wojtek wrote:
> > >>> @ Mike: I'm afraid it wouldn't work, I'm not sure if you get how the
> > >>> phase accumulator works, trust me it is ok the way it is.

>
> > I get the phase accumulator,
> > but why bother with the fussy DCM at all?

>
> > Newman wrote:
> > >> Some people cringe when they see a register output used as an
> > >> input clock to other synchronous logic and will go to great lengths to
> > >> avoid it because they might have to explain why this will never cause
> > >> a timing issue.

>
> > I avoid it because
> > I prefer writing code
> > to writing clock domain constraints.

>
> > > Since most DCM's aren't able to create a frequency
> > > of less than 10MHz, using phase accumulator to do it is pretty good
> > > idea (and it will be quite precise as well).

>
> > I agree.
> > So why did you punt it?
> > A phase accumulator is portable, flexible and a precise as I need.
> > See also:http://groups.google.com/groups/search?q=accum_s

>
> > -- Mike Treseler

>
> Hi Wojtek
>
> I noted with "-- Look Here ZZZ" comments where preliminary changes
> could be
> investigated to eliminate a clock domain. baudTick becomes a
> synchronously delayed
> version of phaseAcc(phaseAccWidth) and can be used to detect the
> rising edge of
> phaseAcc(phaseAccWidth) after a clock cycle delay. I did not
> simulate it or anything.
>
> -- baud generator based on phase accumulator
> baudTickGen : process (clk) is begin
> if(rising_edge(clk))then
> phaseAcc <= phaseAcc + phaseAccTuning;
> baudTick <= phaseAcc(phaseAccWidth); -- Look Here ZZZ
> end if;
> end process baudTickGen;
> -- MSB of phase accumulator generates the proper baud rate
> -- Look Here ZZZ baudTick <= phaseAcc(phaseAccWidth);
>
> -- transmitter: 8 bits of data, no parity control, 1 stop bit
> -- Look Here ZZZ transmitter : process (baudTick) is begin
> transmitter : process (clk) is begin -- Look Here
>
> -- Look HereZZZ if(rising_edge(baudTick))then
> if((baudTick = '0') and (phaseAcc(phaseAccWidth) = '1')) then --
> Look Here ZZZ
> showtick <='1';
> if(reset = '1')then
> state <= 0;
> dataBuffer <= (others => '0');
> else
> if(state = 0 and startTxD = '0')then
> busyTxD <= '0';
> TxD <= '1';
> elsif(state = 0 and startTxD = '1')then
> TxD <= '0';
> dataBuffer <= dataTxD;
> busyTxD <= '1';
> state <= state + 1;
> elsif(state > 0 and state < 9)then
> busyTxD <= '1';
> TxD <= dataBuffer(state-1);
> state <= state + 1;
> elsif(state = 9)then
> TxD <= '1';
> busyTxD <= '1';
> state <= 0;
> end if;
> end if;
>
> end if;
> end process;
>
> end TxD_arch;



it's been far too long since I've written any VHDL, but I verilog I
would do it like this:

reg [phaseAccWidth-1:0] phaseAcc;
reg baudTick;

[email protected](posedge clk or rstb)
if(!rstb)
{baudTick,phaseAcc} <= 0;
else
{baudTick,phaseAcc} <= {1'd0,phaseAcc} + phaseAccTuning;

.....


-Lasse
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  #17 (permalink)  
Old 07-23-2008, 02:45 AM
Newman
Guest
 
Posts: n/a
Default Re: Help to SImulate Uart TX

On Jul 22, 7:23*pm, [email protected] wrote:
> On 22 Jul., 17:00, Newman <[email protected]> wrote:
>
>
>
>
>
> > On Jul 22, 9:43 am, Mike Treseler <[email protected]> wrote:

>
> > > mike wrote:
> > > >>>> A better design would use clk here
> > > >>>> and make baudTick a clock enable.
> > > wojtek wrote:
> > > >>> @ Mike: I'm afraid it wouldn't work, I'm not sure if you get how the
> > > >>> phase accumulator works, trust me it is ok the way it is.

>
> > > I get the phase accumulator,
> > > but why bother with the fussy DCM at all?

>
> > > Newman wrote:
> > > >> Some people cringe when they see a register output used as an
> > > >> input clock to other synchronous logic and will go to great lengths to
> > > >> avoid it because they might have to explain why this will never cause
> > > >> a timing issue.

>
> > > I avoid it because
> > > I prefer writing code
> > > to writing clock domain constraints.

>
> > > > Since most DCM's aren't able to create a frequency
> > > > of less than 10MHz, using phase accumulator to do it is pretty good
> > > > idea (and it will be quite precise as well).

>
> > > I agree.
> > > So why did you punt it?
> > > A phase accumulator is portable, flexible and a precise as I need.
> > > See also:http://groups.google.com/groups/search?q=accum_s

>
> > > * * * * -- Mike Treseler

>
> > Hi Wojtek

>
> > * I noted with "-- Look Here ZZZ" comments where preliminary changes
> > could be
> > investigated to eliminate a clock domain. *baudTick becomes a
> > synchronously delayed
> > version of phaseAcc(phaseAccWidth) and can be used to detect the
> > rising edge of
> > phaseAcc(phaseAccWidth) after a *clock cycle delay. *I did not
> > simulate it or anything.

>
> > -- baud generator based on phase accumulator
> > * baudTickGen : process (clk) is begin
> > * * if(rising_edge(clk))then
> > * * * phaseAcc <= phaseAcc + phaseAccTuning;
> > * * * baudTick <= phaseAcc(phaseAccWidth); * * * *-- Look Here ZZZ
> > * * end if;
> > * end process baudTickGen;
> > * -- MSB of phase accumulator generates the proper baud rate
> > * -- Look Here ZZZ baudTick <= phaseAcc(phaseAccWidth);

>
> > * -- transmitter: 8 bits of data, no parity control, 1 stop bit
> > * -- Look Here ZZZ transmitter : process (baudTick) is begin
> > * transmitter : process (clk) is begin *-- Look Here

>
> > * * -- Look HereZZZ *if(rising_edge(baudTick))then
> > * * if((baudTick = '0') and (phaseAcc(phaseAccWidth) = '1')) then * --
> > Look Here ZZZ
> > * * * * showtick <='1';
> > * * * if(reset = '1')then
> > * * * * state <= 0;
> > * * * * dataBuffer <= (others => '0');
> > * * * else
> > * * * * if(state = 0 and startTxD = '0')then
> > * * * * * busyTxD <= '0';
> > * * * * * TxD <= '1';
> > * * * * elsif(state = 0 and startTxD = '1')then
> > * * * * * TxD <= '0';
> > * * * * * dataBuffer <= dataTxD;
> > * * * * * busyTxD <= '1';
> > * * * * * state <= state + 1;
> > * * * * elsif(state > 0 and state < 9)then
> > * * * * * busyTxD <= '1';
> > * * * * * TxD <= dataBuffer(state-1);
> > * * * * * state <= state + 1;
> > * * * * elsif(state = 9)then
> > * * * * * TxD <= '1';
> > * * * * * busyTxD <= '1';
> > * * * * * state <= 0;
> > * * * * end if;
> > * * * end if;

>
> > * * * * *end if;
> > * end process;

>
> > end TxD_arch;

>
> it's been far too long since I've written any VHDL, but I verilog I
> would do it like this:
>
> reg *[phaseAccWidth-1:0] phaseAcc;
> reg * * * * * * * * * * *baudTick;
>
> [email protected](posedge clk or rstb)
> *if(!rstb)
> * * {baudTick,phaseAcc} <= 0;
> *else
> * * {baudTick,phaseAcc} <= {1'd0,phaseAcc} + phaseAccTuning;
>
> ....
>
> -Lasse- Hide quoted text -
>
> - Show quoted text -


Hi Lasse,
It would appear that your way is clever. It looks to generates a
clock enable pulse on the overflow which would appear to happen only
for one clk cycle, and it also has a reset which would make the
simulation a easier. Took me a minute to determine what you were
doing.

I did not mean to get involved with recoding the designer's file. I
thought there was some communications snafu of what was meant by using
baudTick as a clock enable. My attempt was to try to give a little
better understanding of what was involved and kindof show that it was
not a big change. I think your code does this better. With that, I
shall exit this thread

-Regards

Newman

-Newman
Reply With Quote
  #18 (permalink)  
Old 07-23-2008, 07:54 AM
wojtek
Guest
 
Posts: n/a
Default Re: Help to SImulate Uart TX

I'am always open for new ideas how to code certain things, but for now
I will probably stick with my code (since I've written small software
to automatically generate VHDL for certain input/output frequencies),
in future I will probably switch to Verilog and update files on my
page with Verilog files instead of VHDL. But such suggestions are
always helpful and welcome

Regards

Newman napisał(a):
> On Jul 22, 7:23�pm, [email protected] wrote:
> > On 22 Jul., 17:00, Newman <[email protected]> wrote:
> >
> >
> >
> >
> >
> > > On Jul 22, 9:43 am, Mike Treseler <[email protected]> wrote:

> >
> > > > mike wrote:
> > > > >>>> A better design would use clk here
> > > > >>>> and make baudTick a clock enable.
> > > > wojtek wrote:
> > > > >>> @ Mike: I'm afraid it wouldn't work, I'm not sure if you get how the
> > > > >>> phase accumulator works, trust me it is ok the way it is.

> >
> > > > I get the phase accumulator,
> > > > but why bother with the fussy DCM at all?

> >
> > > > Newman wrote:
> > > > >> Some people cringe when they see a register output used as an
> > > > >> input clock to other synchronous logic and will go to great lengths to
> > > > >> avoid it because they might have to explain why this will never cause
> > > > >> a timing issue.

> >
> > > > I avoid it because
> > > > I prefer writing code
> > > > to writing clock domain constraints.

> >
> > > > > Since most DCM's aren't able to create a frequency
> > > > > of less than 10MHz, using phase accumulator to do it is pretty good
> > > > > idea (and it will be quite precise as well).

> >
> > > > I agree.
> > > > So why did you punt it?
> > > > A phase accumulator is portable, flexible and a precise as I need.
> > > > See also:http://groups.google.com/groups/search?q=accum_s

> >
> > > > � � � � -- Mike Treseler

> >
> > > Hi Wojtek

> >
> > > � I noted with "-- Look Here ZZZ" comments where preliminary changes
> > > could be
> > > investigated to eliminate a clock domain. �baudTick becomes a
> > > synchronously delayed
> > > version of phaseAcc(phaseAccWidth) and can be used to detect the
> > > rising edge of
> > > phaseAcc(phaseAccWidth) after a �clock cycle delay. �I did not
> > > simulate it or anything.

> >
> > > -- baud generator based on phase accumulator
> > > � baudTickGen : process (clk) is begin
> > > � � if(rising_edge(clk))then
> > > � � � phaseAcc <= phaseAcc + phaseAccTuning;
> > > � � � baudTick <= phaseAcc(phaseAccWidth); � � � �-- Look Here ZZZ
> > > � � end if;
> > > � end process baudTickGen;
> > > � -- MSB of phase accumulator generates the proper baud rate
> > > � -- Look Here ZZZ baudTick <= phaseAcc(phaseAccWidth);

> >
> > > � -- transmitter: 8 bits of data, no parity control, 1 stop bit
> > > � -- Look Here ZZZ transmitter : process (baudTick) is begin
> > > � transmitter : process (clk) is begin �-- Look Here

> >
> > > � � -- Look HereZZZ �if(rising_edge(baudTick))then
> > > � � if((baudTick = '0') and (phaseAcc(phaseAccWidth) = '1')) then � --
> > > Look Here ZZZ
> > > � � � � showtick <='1';
> > > � � � if(reset = '1')then
> > > � � � � state <= 0;
> > > � � � � dataBuffer <= (others => '0');
> > > � � � else
> > > � � � � if(state = 0 and startTxD = '0')then
> > > � � � � � busyTxD <= '0';
> > > � � � � � TxD <= '1';
> > > � � � � elsif(state = 0 and startTxD = '1')then
> > > � � � � � TxD <= '0';
> > > � � � � � dataBuffer <= dataTxD;
> > > � � � � � busyTxD <= '1';
> > > � � � � � state <= state + 1;
> > > � � � � elsif(state > 0 and state < 9)then
> > > � � � � � busyTxD <= '1';
> > > � � � � � TxD <= dataBuffer(state-1);
> > > � � � � � state <= state + 1;
> > > � � � � elsif(state = 9)then
> > > � � � � � TxD <= '1';
> > > � � � � � busyTxD <= '1';
> > > � � � � � state <= 0;
> > > � � � � end if;
> > > � � � end if;

> >
> > > � � � � �end if;
> > > � end process;

> >
> > > end TxD_arch;

> >
> > it's been far too long since I've written any VHDL, but I verilog I
> > would do it like this:
> >
> > reg �[phaseAccWidth-1:0] phaseAcc;
> > reg � � � � � � � � � � �baudTick;
> >
> > [email protected](posedge clk or rstb)
> > �if(!rstb)
> > � � {baudTick,phaseAcc} <= 0;
> > �else
> > � � {baudTick,phaseAcc} <= {1'd0,phaseAcc} + phaseAccTuning;
> >
> > ....
> >
> > -Lasse- Hide quoted text -
> >
> > - Show quoted text -

>
> Hi Lasse,
> It would appear that your way is clever. It looks to generates a
> clock enable pulse on the overflow which would appear to happen only
> for one clk cycle, and it also has a reset which would make the
> simulation a easier. Took me a minute to determine what you were
> doing.
>
> I did not mean to get involved with recoding the designer's file. I
> thought there was some communications snafu of what was meant by using
> baudTick as a clock enable. My attempt was to try to give a little
> better understanding of what was involved and kindof show that it was
> not a big change. I think your code does this better. With that, I
> shall exit this thread
>
> -Regards
>
> Newman
>
> -Newman

Reply With Quote
  #19 (permalink)  
Old 07-24-2008, 06:30 PM
Guest
 
Posts: n/a
Default Re: Help to SImulate Uart TX

On 23 Jul., 07:54, wojtek <[email protected]> wrote:
> I'am always open for new ideas how to code certain things, but for now
> I will probably stick with my code (since I've written small software
> to automatically generate VHDL for certain input/output frequencies),
> in future I will probably switch to Verilog and update files on my
> page with Verilog files instead of VHDL. But such suggestions are
> always helpful and welcome
>
> Regards
>

snip

hi,

The point wasn't that you should change to verilog or make a lot of
changes, just that the minor change of making the phase accumulator
produce a clock enable and
running everything on the same clock would make it a lot easier to
integrate in a design, because it would avoid an extra clock domain
and all the potential problems with that.

-Lasse
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