On 4 Aug 2004 23:27:02 -0700,
[email protected] (Kiran) wrote:
>Hi Allan,
>
>> Obviously rules of thumb are based around certain assumptions. You
>> need to know how fast your chip is (w.r.t. your clock rate), whether
>> you are doing floorplanning, etc.
>
>You are right. It depends on device, required clock rate, design etc.
>
>How do you control fan-out? Is it through a tool-setting or through
>coding style itself?
I use coding style. For example, if my source code has a signal
feeding eight other LUTs, I know that the fanout is eight.
Note that for most designs (which aren't pushing the technology to the
limits) it's quite reasonable to ignore fanout in your source code and
rely on the fanout limit in your synthesiser. This should have a
default of 50-100 or so. It will replicate logic to maintain this
limit. E.g. if the fanout limit is 100 and you have 200 loads on a
flip flop, the synthesiser will replicate the flip flop (so that there
are two flip flops fed with identical inputs) and each flip flop will
drive 100 loads.
My experience is that automatic replication makes floorplanning
harder.
>> Note that FPGA flip flops are basically free. Don't be afraid to use
>> them to make the routing easier.
>
>This is not very clear. Do you mean that we should insert registers in
>the paths in the RTL code?
Yes.
>> This one is fairly good, although floorplanning (good or bad) can make
>> a difference. Note that a tightly packed part will often produce a
>> few excessively long delays due to routing congestion.
>
>Is there a thumb rule with respect to device occupancy? Should it be
>restricted to say 75% of the device so that routing does not get
>congested?
The obvious hard limit is 100% (although I once had Maxplus make some
FFs out of comb. logic in a CPLD so that I actually used more than
100% of the flip flops in the device!).
A practical limit is 50% to 100%. I've never seen anyone suggest a
utilisation of less than 50%.
There is also a tradeoff with development time. Lower utilisation
means faster build times. I've seen projects which have had larger
FPGA on the prototypes (to speed code development) and smaller FPGAs
on the production units (to lower costs). This is also important if
the requirments for your project are not fully understood- you have
room to manoeuver during development.
A lot depends on your design. It may end up being flip flop limited
(which would be unusual in an
FPGA, but more common in a CPLD), or it
may be block ram limited, etc.
My current chip is using most of the block ram but only about 40% of
the FFs and logic. YMMV.
Regards,
Allan.