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  #1 (permalink)  
Old 11-28-2007, 10:06 AM
Nial Stewart
Guest
 
Posts: n/a
Default Gnd plane coupling with DDR routing from FPGA <-> DDR?

Hopefully some of you guys who have gone through this can
comment...

We're doing our first board with a couple of DDRs and have a
query with ground plane coupling when routing the signals out
of the FPGA.

We're hoping to get away with a 6 layer board so the stack is..

sig1
GND
sig2
sig3
PWR
sig4

Any signals that're routed from the FPBA ball to sig4 won't have
the same good GND return paths to the FPGA that those coming out
on sig1/sig2 will have.

We're aiming to run the interface at ~2* 120MHz.

We don't have any simulation tools so are having to design using best
practice.

We can place a GND island in on the PWR layer under the FPGA/DDR
with plenty of vias stitching it up to the 'real' GND plane, but
this will make the PWR routing more difficult.

Does this matter, will the difference in GND coupling be a problem?

Some of the app notes we've read suggest that the track impedance
isn't too much of a problem.


Thanks for any pointers,


Nial




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  #2 (permalink)  
Old 11-28-2007, 11:22 AM
Brian Drummond
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Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?

On Wed, 28 Nov 2007 10:06:22 -0000, "Nial Stewart"
<nial*REMOVE_THIS*@nialstewartdevelopments.co.uk > wrote:

>Hopefully some of you guys who have gone through this can
>comment...


I haven't yet, but I'm asking myself the same sort of questions for the
same sort of reasons.

>We're hoping to get away with a 6 layer board so the stack is..


Just an opinion.

While the board may be routable on 6 layers ...

check the incremental cost of 8 layers over 6. Sometimes it's 10% or
less.

That gives you a second ground plane and allows you to improve power
distribution.

Unless this is a HIGHLY cost-sensitive product, that looks like a good
investment to me, given the cost of the time involved in engineering a
solution any more closely.

- Brian
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  #3 (permalink)  
Old 11-28-2007, 03:36 PM
austin
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Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?

Nial,

Get a Signal Integrity Tool.

The money you spend on that is recovered by NOT having to respin your
pcb and first assembly run ONE TIME.

For something that has guaranteed payback, for the cost of a respin in
materials alone (does not even include your time, the pcb designer's
time, your cost of lost opportunity being late to market...) why do
people choose to suffer?

Are you a masochist? Do you enjoy pain? Or are you a sadist? Do you
enjoy causing pain to others?

I suppose if I wanted revenge on a horrible boss, I would just follow
their directions, but what is the fun in that? Go work for someone who
has a brain.

Austin
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  #4 (permalink)  
Old 11-28-2007, 04:58 PM
David Spencer
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Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?


"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk > wrote in
message news:[email protected]

>
> We can place a GND island in on the PWR layer under the FPGA/DDR
> with plenty of vias stitching it up to the 'real' GND plane, but
> this will make the PWR routing more difficult.
>
> Does this matter, will the difference in GND coupling be a problem?
>
>
> Nial
>


I would never split a plane except as a last resort (unless you can sandwich
it between two solid planes - I often use a four layer GND, split power,
split power, GND sandwich in the middle of 16-20 layer boards), because of
the issues with traces crossing the split. If you must stick to six layers
then you need to make the power plane look like a ground plane by ensuring
that there are adequate decoupling capacitors spread uniformly across the
board, such that no point on the board is more than some short distance from
a capacitor. The AC return current can flow along the power plane and
through the capacitor to ground. Of course, you want to reduce the
inductance so use 0402 or 0603 parts with vias very close to the pads.


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  #5 (permalink)  
Old 11-28-2007, 05:15 PM
Nico Coesel
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Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?

"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk >
wrote:

>Hopefully some of you guys who have gone through this can
>comment...
>
>We're doing our first board with a couple of DDRs and have a
>query with ground plane coupling when routing the signals out
>of the FPGA.
>
>We're hoping to get away with a 6 layer board so the stack is..
>
>sig1
>GND
>sig2
>sig3
>PWR
>sig4
>
>Any signals that're routed from the FPBA ball to sig4 won't have
>the same good GND return paths to the FPGA that those coming out
>on sig1/sig2 will have.
>
>We're aiming to run the interface at ~2* 120MHz.


I have designed a similar 4 layer board which runs DDR at 100MHz. As
long as the traces between the FPGA and the DDR memory do not cross
plane borders, you'll probably be fine. In my design I optimized the
connections so I did have at most one via close to the FPGA pin in
traces between the FPGA and DDR.

--
Reply to [email protected] (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl
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  #6 (permalink)  
Old 11-28-2007, 05:31 PM
KJ
Guest
 
Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?

On Nov 28, 5:06 am, "Nial Stewart"
<nial*[email protected] > wrote:
> Hopefully some of you guys who have gone through this can
> comment...
>
> We're doing our first board with a couple of DDRs and have a
> query with ground plane coupling when routing the signals out
> of the FPGA.
>
> We're hoping to get away with a 6 layer board so the stack is..
>
> sig1
> GND
> sig2
> sig3
> PWR
> sig4
>

Power and ground are not going to be forming a very good capacitor to
supply power so you're making a big compromise right there, it won't
be a really low inductance pathway to deliver power to the parts on
the board. Ideally you'd like to have two more layers, move PWR up to
be underneath GND and then mirror that on the bottom side (i.e. sig1,
GND, PWR, sig2, sig3, PWR, GND, sig4). Whether your 6 layer bites you
or not will depend entirely on how much switching is going on and how
demanding the parts are. I recently consulted on a design that had
the above type of stackup and the PCB was unable to deliver enough
3.3V to the FPGA and would cause it to functionally upset, the board
failed. Adding the planes and putting power adjacent to ground was
the biggest impact in the fix, other remedies that were tried to band
aid the boards while waiting for the improved stackup design had only
marginal impact.

> Any signals that're routed from the FPBA ball to sig4 won't have
> the same good GND return paths to the FPGA that those coming out
> on sig1/sig2 will have.

As long as you're not talking about signals having to cross a break in
the power plane itself, being adjacent to the cut up power plane is
not much different. It all comes down to how much copper is on that
plane adjacent to the signal. The electromagnetic field does not care
the voltage level on the hunk of metal that it runs into first.

>
> We're aiming to run the interface at ~2* 120MHz.
>

Is that 2 DDRs at 120 MHz? Or 240 MHz?

> We don't have any simulation tools so are having to design using best
> practice.
>

If you can't spring for si tools, then I'd suggest the following
resources that you should peruse in besides just this particular
newsgroup
1. "Right the First Time: A Practical Handbook on High Speed PCB
Design and System Design". Volumes 1 and 2, by Lee W. Ritchey. Each
will set you back about $90USD I think but they are both well worth
it. Can be purchased from speedingedge.com (I have no financial or
other interest in the book or the Speeding Edge company, this is just
a recommendation for what I've found to be an excellent resource).

2. http://www.freelists.org/list/si-list which is a newsgroup
dedicated to signal integrity issues. Post your questions up there
and you'll get well informed responses from a number of experts.
comp.arch.fpga contains some people that know what they're talking
about and others that only think they know. In fairness though, this
FPGA newsgroup has a different focus that handles issues that run
through the whole spectrum of issues related to FPGA design starting
from synthesis/simulation tool problems, coding formats, downloading,
component packaging and PCB design, etc.

> We can place a GND island in on the PWR layer under the FPGA/DDR
> with plenty of vias stitching it up to the 'real' GND plane, but
> this will make the PWR routing more difficult.
>

Putting the island in won't help at all.

Kevin Jennings
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  #7 (permalink)  
Old 11-28-2007, 06:45 PM
Symon
Guest
 
Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?

"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk > wrote in
message news:[email protected]
> Hopefully some of you guys who have gone through this can
> comment...
>
> We're doing our first board with a couple of DDRs and have a
> query with ground plane coupling when routing the signals out
> of the FPGA.
>
> We're hoping to get away with a 6 layer board so the stack is..
>
> sig1
> GND
> sig2
> sig3
> PWR
> sig4
>
> Any signals that're routed from the FPBA ball to sig4 won't have
> the same good GND return paths to the FPGA that those coming out
> on sig1/sig2 will have.
>
> We're aiming to run the interface at ~2* 120MHz.
>
> We don't have any simulation tools so are having to design using best
> practice.
>
> We can place a GND island in on the PWR layer under the FPGA/DDR
> with plenty of vias stitching it up to the 'real' GND plane, but
> this will make the PWR routing more difficult.
>
> Does this matter, will the difference in GND coupling be a problem?
>
> Some of the app notes we've read suggest that the track impedance
> isn't too much of a problem.
>
>
> Thanks for any pointers,
>
>
> Nial
>

Hi Nial,

Wow, you got some strange answers! (IMHO, natch.) The same old chestnuts
about PWR and GND planes being used as bypass capacitance. Waste of time.
The tiny capacitance is no use to you as you have to attach the FPGA to it
_VIA_ inductance. This is why FPGA companies embed bypass caps in the
package. BTW, what PWR is on the plane? VCCO for your DDR bank? VCCINT?

Also, 16-20 layer boards? I guess it'll work, but I'm glad I'm not paying
for it.

Good answers you got are, 'use two more layers', 'simulate', 'SI-LIST', and
'use as few vias as possible'. Oh, and don't cross gaps in planes, but we
all know that, right?

I'd do something like this:-

sig
gnd
sig
sig
gnd
sig

I'd route the powers on one or two of the internal layers. I'd use copper
pours and/or little puddles of cu for each supply. I'd use X2Y caps backside
of the FPGA for bypassing. (Google X2Y FPGA) If a fast signal changes its
ground reference from one ground plane to another, I'd put a GND via nearby.
Several fast signals can share a single ground via.

Austin's right, if you're a beginner you should certainly use a simulator.
Maybe you can borrow one from somewhere? Any universities nearby? However,
the 'two ground planes' design makes it considerably harder to get it wrong,
especially at 120MHz.

HTH. Syms.

p.s. You did search back through CAF for previous threads, right? ;-)


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  #8 (permalink)  
Old 11-28-2007, 08:58 PM
David Spencer
Guest
 
Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?

"Symon" <[email protected]> wrote in message
news:[email protected]
> Wow, you got some strange answers! (IMHO, natch.) The same old chestnuts
> about PWR and GND planes being used as bypass capacitance. Waste of time.
> The tiny capacitance is no use to you as you have to attach the FPGA to it
> _VIA_ inductance. This is why FPGA companies embed bypass caps in the
> package. BTW, what PWR is on the plane? VCCO for your DDR bank? VCCINT?
>


I disagree, as does most of the research done into the subject. The use of
buried capacitance, typically by having adjacent power and ground planes
separated by as small a distance as possible (2 thou is normal), has been
shown to be very favorable when compared to discrete decoupling caps because
although the capacitance is much lower the inductance is very much lower so
the overall impedence is significantly lower. There is an article about it
here: http://www.ddmconsulting.com/Design_Guides/bcguide.pdf

The requirement for discrete capacitors on the BGA substrate itself is a
different matter. That is to compensate for the inductance of the BGA ball
and tracking and is necessary regardless of how the board level decoupling
is implemented.


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  #9 (permalink)  
Old 11-28-2007, 10:24 PM
Jon Elson
Guest
 
Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?



Nial Stewart wrote:
> Hopefully some of you guys who have gone through this can
> comment...
>
> We're doing our first board with a couple of DDRs and have a
> query with ground plane coupling when routing the signals out
> of the FPGA.
>
> We're hoping to get away with a 6 layer board so the stack is..
>
> sig1
> GND
> sig2
> sig3
> PWR
> sig4
>

I've had good results with :
sig1
sig2
GND
PWR
sig3
sig4

If you really need to, you can make the traces on sig1 and sig4 a little
wider to keep the impedance near the right value. Keeping GND and PWR
planes close together helps. If sig1 and sig2 are orthogonal, and same
for sig3 and sig4, there should be minimal crosstalk. I have not done a
DDR memory, but signal integrity is signal integrity.

Jon

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  #10 (permalink)  
Old 11-29-2007, 02:33 AM
Didi
Guest
 
Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?

> We're aiming to run the interface at ~2* 120MHz.

I understand that as 120 MHz clock, 240 MHz data rate
during bursts.
Recently I had a similar case - processor (not FPGA),
which is in a 256 ball FPGA, 133 MHz clock/266 MHz data burst
rate.
However, I was much more conservatiive with my stackup.
Instead of your

> sig1
> GND
> sig2
> sig3
> PWR
> sig4


I did 6 layers as well, but my stackup is:

signal
GND
PWR
PWR
GND
signal

Worked the first time, actually see the prototype
(very first one assembled, design for an external customer)
board here:

http://tgi-sci.com/y2demo/PICT3007sc.JPG .

The two DDRAMs (x16 each) are close to the board centre, easy
to spot.

Here is the bare board in some better detail:

http://tgi-sci.com/misc/PICT0605.JPG .

The board is routed at 6 mil most of the time which goes
down to somewhat over 4 mil for the worst case angular
ring and for traces between BGA pads (3 traces between a
pair of 1.27mm spaced pads/vias.
Have used these rules on other boards as well, have never
failed me. Routing takes somewhat more head scratching (or is
it hear teraing... :-) ), but has always been doable.
Now what do I do with a 0.8mm BGA (soon to be routed here,
never done so far) is yet to be seen... :-)

At these low speeds, buying signal integrity tools/consultants
will be a sheer waste. You need neither (although ask that on
the SI list and you will be overwhelmed by suggestions to
buy all things imaginable... make sure to ignore such advice,
the SI tool writers and SI consultants are pretty active on that
list).
Buy a tool by the usual criterion, that is, only if you know
exactly what you want the tool to do for you and if you
understand how it will do it.
Buying a software blindly expecting it to solve your problems
will typically result in more, not less problems. Which does
not mean most people nowadays are not doing exactly that,
of course :-).

Again, 120 MHz is nearly DC nowadays. You don't need any
fancy SI tools to do it.

Dimiter

------------------------------------------------------
Dimiter Popoff Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

On Nov 28, 12:06 pm, "Nial Stewart"
<nial*[email protected] > wrote:
> Hopefully some of you guys who have gone through this can
> comment...
>
> We're doing our first board with a couple of DDRs and have a
> query with ground plane coupling when routing the signals out
> of the FPGA.
>
> We're hoping to get away with a 6 layer board so the stack is..
>
> sig1
> GND
> sig2
> sig3
> PWR
> sig4
>
> Any signals that're routed from the FPBA ball to sig4 won't have
> the same good GND return paths to the FPGA that those coming out
> on sig1/sig2 will have.
>
> We're aiming to run the interface at ~2* 120MHz.
>
> We don't have any simulation tools so are having to design using best
> practice.
>
> We can place a GND island in on the PWR layer under the FPGA/DDR
> with plenty of vias stitching it up to the 'real' GND plane, but
> this will make the PWR routing more difficult.
>
> Does this matter, will the difference in GND coupling be a problem?
>
> Some of the app notes we've read suggest that the track impedance
> isn't too much of a problem.
>
> Thanks for any pointers,
>
> Nial


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  #11 (permalink)  
Old 11-29-2007, 04:14 AM
Didi
Guest
 
Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?

> Have used these rules on other boards as well, have never
> failed me. Routing takes somewhat more head scratching (or is
> it hear teraing... :-) )


Sorry for the typos above, it should read
"or is it hair tearing"...

On Nov 29, 4:33 am, Didi <[email protected]> wrote:
> > We're aiming to run the interface at ~2* 120MHz.

>
> I understand that as 120 MHz clock, 240 MHz data rate
> during bursts.
> Recently I had a similar case - processor (not FPGA),
> which is in a 256 ball FPGA, 133 MHz clock/266 MHz data burst
> rate.
> However, I was much more conservatiive with my stackup.
> Instead of your
>
> > sig1
> > GND
> > sig2
> > sig3
> > PWR
> > sig4

>
> I did 6 layers as well, but my stackup is:
>
> signal
> GND
> PWR
> PWR
> GND
> signal
>
> Worked the first time, actually see the prototype
> (very first one assembled, design for an external customer)
> board here:
>
> http://tgi-sci.com/y2demo/PICT3007sc.JPG.
>
> The two DDRAMs (x16 each) are close to the board centre, easy
> to spot.
>
> Here is the bare board in some better detail:
>
> http://tgi-sci.com/misc/PICT0605.JPG.
>
> The board is routed at 6 mil most of the time which goes
> down to somewhat over 4 mil for the worst case angular
> ring and for traces between BGA pads (3 traces between a
> pair of 1.27mm spaced pads/vias.
> Have used these rules on other boards as well, have never
> failed me. Routing takes somewhat more head scratching (or is
> it hear teraing... :-) ), but has always been doable.
> Now what do I do with a 0.8mm BGA (soon to be routed here,
> never done so far) is yet to be seen... :-)
>
> At these low speeds, buying signal integrity tools/consultants
> will be a sheer waste. You need neither (although ask that on
> the SI list and you will be overwhelmed by suggestions to
> buy all things imaginable... make sure to ignore such advice,
> the SI tool writers and SI consultants are pretty active on that
> list).
> Buy a tool by the usual criterion, that is, only if you know
> exactly what you want the tool to do for you and if you
> understand how it will do it.
> Buying a software blindly expecting it to solve your problems
> will typically result in more, not less problems. Which does
> not mean most people nowadays are not doing exactly that,
> of course :-).
>
> Again, 120 MHz is nearly DC nowadays. You don't need any
> fancy SI tools to do it.
>
> Dimiter
>
> ------------------------------------------------------
> Dimiter Popoff Transgalactic Instruments
>
> http://www.tgi-sci.com
> ------------------------------------------------------
>
> On Nov 28, 12:06 pm, "Nial Stewart"
>
> <nial*[email protected] > wrote:
> > Hopefully some of you guys who have gone through this can
> > comment...

>
> > We're doing our first board with a couple of DDRs and have a
> > query with ground plane coupling when routing the signals out
> > of the FPGA.

>
> > We're hoping to get away with a 6 layer board so the stack is..

>
> > sig1
> > GND
> > sig2
> > sig3
> > PWR
> > sig4

>
> > Any signals that're routed from the FPBA ball to sig4 won't have
> > the same good GND return paths to the FPGA that those coming out
> > on sig1/sig2 will have.

>
> > We're aiming to run the interface at ~2* 120MHz.

>
> > We don't have any simulation tools so are having to design using best
> > practice.

>
> > We can place a GND island in on the PWR layer under the FPGA/DDR
> > with plenty of vias stitching it up to the 'real' GND plane, but
> > this will make the PWR routing more difficult.

>
> > Does this matter, will the difference in GND coupling be a problem?

>
> > Some of the app notes we've read suggest that the track impedance
> > isn't too much of a problem.

>
> > Thanks for any pointers,

>
> > Nial


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  #12 (permalink)  
Old 11-29-2007, 06:16 AM
John Larkin
Guest
 
Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?

On Wed, 28 Nov 2007 10:06:22 -0000, "Nial Stewart"
<nial*REMOVE_THIS*@nialstewartdevelopments.co.uk > wrote:

>Hopefully some of you guys who have gone through this can
>comment...
>
>We're doing our first board with a couple of DDRs and have a
>query with ground plane coupling when routing the signals out
>of the FPGA.
>
>We're hoping to get away with a 6 layer board so the stack is..
>
>sig1
>GND
>sig2
>sig3
>PWR
>sig4
>
>Any signals that're routed from the FPBA ball to sig4 won't have
>the same good GND return paths to the FPGA that those coming out
>on sig1/sig2 will have.
>
>We're aiming to run the interface at ~2* 120MHz.
>
>We don't have any simulation tools so are having to design using best
>practice.
>
>We can place a GND island in on the PWR layer under the FPGA/DDR
>with plenty of vias stitching it up to the 'real' GND plane, but
>this will make the PWR routing more difficult.
>
>Does this matter, will the difference in GND coupling be a problem?
>
>Some of the app notes we've read suggest that the track impedance
>isn't too much of a problem.
>
>
>Thanks for any pointers,
>
>
>Nial
>
>
>


As Jon suggests, putting power and ground adjacent is generally a bit
better.

But either stackup will work fine. As long as the power plane (or its
split pours) is pretty well bypassed to ground, the signals can't tell
the difference between them or ground as the "return" plane. If power
and ground are adjacent layers, the increased plane-plane capacitance
keeps them a bit more equipotential at very high frequencies.

Don't worry about signals crossing small slits on a split power plane;
that is simply not an issue in real life. You can barely resolve
crossings like that on a 20 GHz TDR... it's down in the wiggles caused
by the fiberglass weave.

We've done pretty hairy stuff with Xilinx bga's on 6 layers, with no
signal integrity problems.

The thing to watch out for is signal-signal crosstalk, especially on
clock lines. Clocks need especially serious signal integrity treatment
these days. And "clocks" includes CCLK!

I suppose I could post some layer pics...


John



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  #13 (permalink)  
Old 11-29-2007, 08:33 AM
John Adair
Guest
 
Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?

Nial

I would expect from our experience that the DDR could be routed in 3
layers assuming you are attaching to a FPGA and a sensible pinout is
chosen. Our product Tarfessock1 achieves the connection of a DDR2 chip
in principally 2 layers with a couple of straggler signals on a 3rd
layer. If this product was a less compoonent dense product we
certainly would do it all in the 2 layers.

Taking that as a starting point you could use one of your tracking
layers as a localised ground layer using a polygon fill and you can
have a fairly good electrical setup for high speed signals. We use
some of the recomendations in Xilinx XAPP693 for layer structure and
never had an issue.We don't use all the recomendations of this
applications note as they are impractical to achieve on a cost
sensitive board.

Signal integrity tools are a nice toy but they are only as good as the
information fed into them. There are generally also expensive although
you can argue that against the cost of a failed board. Even if you
know your pcb manufacturer at this point, and the materials they use
specifically, then at best things like the dielectric constants and
layer spacing vary a lot over product batches unless you pay a lot to
get boards made to an exact specification and get them tested with
resultant yield drop and cost implications. I doubt that any PC
motherboard manufactures ever do that and they make an awful lot of
boards. Those boards also tend to be 4 layers or sometimes 6 layers.

John Adair
Enterpoint Ltd. - Home of Darnaw1. The PGA FPGA solution.

On 28 Nov, 10:06, "Nial Stewart"
<nial*[email protected] > wrote:
> Hopefully some of you guys who have gone through this can
> comment...
>
> We're doing our first board with a couple of DDRs and have a
> query with ground plane coupling when routing the signals out
> of the FPGA.
>
> We're hoping to get away with a 6 layer board so the stack is..
>
> sig1
> GND
> sig2
> sig3
> PWR
> sig4
>
> Any signals that're routed from the FPBA ball to sig4 won't have
> the same good GND return paths to the FPGA that those coming out
> on sig1/sig2 will have.
>
> We're aiming to run the interface at ~2* 120MHz.
>
> We don't have any simulation tools so are having to design using best
> practice.
>
> We can place a GND island in on the PWR layer under the FPGA/DDR
> with plenty of vias stitching it up to the 'real' GND plane, but
> this will make the PWR routing more difficult.
>
> Does this matter, will the difference in GND coupling be a problem?
>
> Some of the app notes we've read suggest that the track impedance
> isn't too much of a problem.
>
> Thanks for any pointers,
>
> Nial


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  #14 (permalink)  
Old 11-29-2007, 08:51 AM
Nial Stewart
Guest
 
Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?

> Nial,
> Get a Signal Integrity Tool.
> The money you spend on that is recovered by NOT having to respin your
> pcb and first assembly run ONE TIME.
> For something that has guaranteed payback, for the cost of a respin in
> materials alone (does not even include your time, the pcb designer's
> time, your cost of lost opportunity being late to market...) why do
> people choose to suffer?



Thanks for the constructive suggestions Austin, in reply to...

> Are you a masochist? Do you enjoy pain? Or are you a sadist? Do you
> enjoy causing pain to others?


...I'm tempted to say "Yes, I have used Xilinx devices in the past".

But that's just me being cheeky.


> I suppose if I wanted revenge on a horrible boss, I would just follow
> their directions, but what is the fun in that? Go work for someone who
> has a brain.


I am the boss.

It's easy enough to spout off when you've all the resources of Xilinx
behind you, the situation in a small (2 man) company is a bit different.

In the UK we generally pay the same price in GBP that you guys pay
in dollars for tools. That makes them twice the price, not so cheap.

We'd then be starting the (presmably long if they're any good) learning
curve to produce useful results for something that we're possibly
only going to be doing once in a blue moon. I doubt we'd be getting
any results defore Christmas.

As others have said this is an almost run of the mill routing/termination
problem, I'm confident we'll get it right with a bit of thought.


Nial.



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  #15 (permalink)  
Old 11-29-2007, 08:57 AM
Nial Stewart
Guest
 
Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?

> I disagree, as does most of the research done into the subject. The use of buried capacitance,
> typically by having adjacent power and ground planes separated by as small a distance as possible
> (2 thou is normal), has been shown to be very favorable when compared to discrete decoupling caps
> because although the capacitance is much lower the inductance is very much lower so the overall
> impedence is significantly lower. There is an article about it here:
> http://www.ddmconsulting.com/Design_Guides/bcguide.pdf


David,

I too am skeptical about the amount of decoupling that close GND/PWR plane
coupling can provice.

In that atricle above they quote 560pF/sq inch. Most BGAs are smaller
than that.

The article suggests that this sort of capacitance is useful for 'random'
logic where there's little synchronisation between gates drawing power.

We're using FPGAs that tend to be largely synchronous.


Page 24 says...

> Memory ICís: Memory ICís generally are assembled in synchronous arrays.
> When these arrays are clocked, a large amount of switching current is required to
> drive the output interfaces and charge the internal memory arrayís. These
> devices require a large amount of high speed current which is larger than BC
> layers can provide. Additional discrete decoupling capacitors will be required.



?

I think I'll rely on my decouplers, the X2Y devices Symon pointed out (again)
seem useful.


Nial.


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  #16 (permalink)  
Old 11-29-2007, 09:07 AM
Nial Stewart
Guest
 
Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?

Hi Symon,

I was hoping you'd stick your oar in!

> Also, 16-20 layer boards? I guess it'll work, but I'm glad I'm not paying for it.


Indeed, this is self funded so I'd like ot keep costs down where possible
(with the proviso things should work).

> Good answers you got are, 'use two more layers'


8 Layers is the brute force answer to the problem. It should definitely
work, but it would be good to find a more elegant solution to the problem.

> , 'simulate', 'SI-LIST', and 'use as few vias as possible'. Oh, and don't cross gaps in planes,
> but we all know that, right?


To use a Belfast expression

"Do you think I came up the Lagan in a bubble?".

No (adjacent) plane splits will be crossed.

> I'd do something like this:-
>
> sig
> gnd
> sig
> sig
> gnd
> sig
>
> I'd route the powers on one or two of the internal layers. I'd use copper pours and/or little
> puddles of cu for each supply.


I think you've said before that you've got away with routing power in like
this with no problems.

> I'd use X2Y caps backside of the FPGA for bypassing. (Google X2Y FPGA)


They look good, and as they're available from Digikey they might be a goer.

The downside is that we're currently using 0402's with round pads on the back
of the board so they fit neatly just at the PWR/GND pins.

The X2Ys would have to be round the edges, but it could be worth adding a
few in.

> If a fast signal changes its ground reference from one ground plane to another, I'd put a GND via
> nearby. Several fast signals can share a single ground via.


The idea was to create a localised GND plane on the PWR layer with vias to
the 'real' GND layer and a matching linking via beside any point at which
a trace goes from the bottom layer to top layer.

> Austin's right, if you're a beginner you should certainly use a simulator. Maybe you can borrow
> one from somewhere? Any universities nearby? However, the 'two ground planes' design makes it
> considerably harder to get it wrong, especially at 120MHz.


But as others have said, 120MHz is almost DC these days!

> p.s. You did search back through CAF for previous threads, right? ;-)


Oh aye, there wasn't too much about routing to DDRs specifically but as
usual all advice was conflicting as here!

:-)

Thansk,

Nial.




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  #17 (permalink)  
Old 11-29-2007, 09:25 AM
Nial Stewart
Guest
 
Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?

> I would never split a plane except as a last resort (unless you can sandwich it between two solid
> planes - I often use a four layer GND, split power, split power, GND sandwich in the middle of
> 16-20 layer boards), because of the issues with traces crossing the split.


As you say below signals can use the PWR plane as a 'pseudo gnd'.

By using this stack are you not loosing the ability to route two internal
signal layers adjacent to the GND planes, and the additional use of the
PWR planes as pseudo grounds?


> If you must stick to six layers then you need to make the power plane look like a ground plane by
> ensuring that there are adequate decoupling capacitors spread uniformly across the board, such
> that no point on the board is more than some short distance from a capacitor. The AC return
> current can flow along the power plane and through the capacitor to ground. Of course, you want to
> reduce the inductance so use 0402 or 0603 parts with vias very close to the pads.


That's a thought. The bank of the FPGA driving the DDR and the device itself
are on the same unbroken power plane. There's also plenty of decoupling
round both devices so we might be OK.


Nial.


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  #18 (permalink)  
Old 11-29-2007, 09:29 AM
Nial Stewart
Guest
 
Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?

> I've had good results with :
> sig1
> sig2
> GND
> PWR
> sig3
> sig4


Are you not missing out on one layer closely coupling to the GND
and using the PWR as a pseudo GND like this?


> If you really need to, you can make the traces on sig1 and sig4 a little wider to keep the
> impedance near the right value. Keeping GND and PWR planes close together helps. If sig1 and
> sig2 are orthogonal, and same
> for sig3 and sig4, there should be minimal crosstalk. I have not done a
> DDR memory, but signal integrity is signal integrity.


Indeed.


Nial.


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  #19 (permalink)  
Old 11-29-2007, 09:37 AM
Nial Stewart
Guest
 
Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?

> I did 6 layers as well, but my stackup is:
>
> signal
> GND
> PWR
> PWR
> GND
> signal


>:-0


That's not very routing efficient.

> Worked the first time, actually see the prototype
> (very first one assembled, design for an external customer)
> board here:
> http://tgi-sci.com/y2demo/PICT3007sc.JPG .
> The two DDRAMs (x16 each) are close to the board centre, easy
> to spot.
> Here is the bare board in some better detail:
> http://tgi-sci.com/misc/PICT0605.JPG .
> The board is routed at 6 mil most of the time which goes
> down to somewhat over 4 mil for the worst case angular
> ring and for traces between BGA pads (3 traces between a
> pair of 1.27mm spaced pads/vias.
> Have used these rules on other boards as well, have never
> failed me. Routing takes somewhat more head scratching (or is
> it hear teraing... :-) ), but has always been doable.
> Now what do I do with a 0.8mm BGA (soon to be routed here,
> never done so far) is yet to be seen... :-)


Thanks for this info.

We've been working from a Micron app note which suggests 8 mil
min clearances between data lines.

On the other hand this is a short point to point connection so
we can probably get away with a lot more than others with more
onerous topologies.

> At these low speeds, buying signal integrity tools/consultants
> will be a sheer waste. You need neither (although ask that on
> the SI list and you will be overwhelmed by suggestions to
> buy all things imaginable... make sure to ignore such advice,
> the SI tool writers and SI consultants are pretty active on that
> list).


Thanks for an alternative viewpoint.

> Again, 120 MHz is nearly DC nowadays. You don't need any
> fancy SI tools to do it.


Hopefully.



Nial.


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  #20 (permalink)  
Old 11-29-2007, 09:42 AM
Nial Stewart
Guest
 
Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?

> Power and ground are not going to be forming a very good capacitor to
> supply power so you're making a big compromise right there, it won't
> be a really low inductance pathway to deliver power to the parts on
> the board.


As below, I'm not convinced this is a problem.

Good _enough_ supply paths with sufficient local decoupling should do?

> Ideally you'd like to have two more layers, move PWR up to
> be underneath GND and then mirror that on the bottom side (i.e. sig1,
> GND, PWR, sig2, sig3, PWR, GND, sig4). Whether your 6 layer bites you
> or not will depend entirely on how much switching is going on and how
> demanding the parts are. I recently consulted on a design that had
> the above type of stackup and the PCB was unable to deliver enough
> 3.3V to the FPGA and would cause it to functionally upset, the board
> failed.


Might it not have been due to bad signal return path integrity or
insufficient grounding?

(I'm not arguing here, just posing the question).


> If you can't spring for si tools, then I'd suggest the following
> resources that you should peruse in besides just this particular
> newsgroup
> 1. "Right the First Time: A Practical Handbook on High Speed PCB
> Design and System Design". Volumes 1 and 2, by Lee W. Ritchey. Each
> will set you back about $90USD I think but they are both well worth
> it. Can be purchased from speedingedge.com (I have no financial or
> other interest in the book or the Speeding Edge company, this is just
> a recommendation for what I've found to be an excellent resource).



Alan (if you're reading this), guess what you're getting for Christmas!


Thanks for the pointers Kevin,


Nial.


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  #21 (permalink)  
Old 11-29-2007, 09:44 AM
Nial Stewart
Guest
 
Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?

> The thing to watch out for is signal-signal crosstalk, especially on
> clock lines. Clocks need especially serious signal integrity treatment
> these days. And "clocks" includes CCLK!



We've been following one of the Micron app notes here, especially wrt
the clocks. It's a fairly short pt to pt connection so hopefully we
should be OK.

Thanks,

Nial.


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  #22 (permalink)  
Old 11-29-2007, 09:50 AM
Nial Stewart
Guest
 
Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?

> I would expect from our experience that the DDR could be routed in 3
> layers assuming you are attaching to a FPGA and a sensible pinout is
> chosen. Our product Tarfessock1 achieves the connection of a DDR2 chip
> in principally 2 layers with a couple of straggler signals on a 3rd
> layer. If this product was a less compoonent dense product we
> certainly would do it all in the 2 layers.


I'm not doing the routing but I think it'll all come out on 3 layers.
We have a few spare pins in the banks we're using so should be able to
shuffle things about.

> Taking that as a starting point you could use one of your tracking
> layers as a localised ground layer using a polygon fill and you can
> have a fairly good electrical setup for high speed signals. We use
> some of the recomendations in Xilinx XAPP693 for layer structure and
> never had an issue.We don't use all the recomendations of this
> applications note as they are impractical to achieve on a cost
> sensitive board.


We'll have a look at that, although I think we've been overly paranoid.
Top and layer 3 are tightly coupled to the GND plane, the bottom layer
should be coupled to the PWR plane if we make sure it's sufficiently
decoupled (as elsewhere in the thread).

> I doubt that any PC
> motherboard manufactures ever do that and they make an awful lot of
> boards. Those boards also tend to be 4 layers or sometimes 6 layers.


Aye, but they are purveyors of magic!

Looking at the complexity/density/performance of a typical PC motherboard
I'm still impressed at the price they knock them out for.

Thanks John.


Nial.


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  #23 (permalink)  
Old 11-29-2007, 11:02 AM
Didi
Guest
 
Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?

> > I did 6 layers as well, but my stackup is:
>
> > signal
> > GND
> > PWR
> > PWR
> > GND
> > signal
> >:-0

>
> That's not very routing efficient.
>


Well at first sight it is not indeed. But take into account
the fact, that you have no hidden signal layers and related
nightmares for errors to fix on the prototype board there
(which does not save you the nightmares of misconnected
power planes... so far I have had the only the latter,
thankfully never to come true :-) ), then think that at the
6/4 mil rules you can do a lot of things (I forgot to mention
it, I do 0.3 or 0.2mm drilling for vias/BGA pads), and
it becomes a lot more attractive.
Especially if you cannot afford a respin of the prototype
(usually the case with me, and thanfully never needed
one - although typically my second or third revision is 100%
error free).

Actually here is one prototype (recent shot of a 5-6 years
old prototype, the CPU cooler got unstuck and I took the
opportunity):

http://tgi-sci.com/misc/PICT3084.JPG

Routed using the same technique, not much free area left
(especially if you count the 5 SDRAM chips on the bottom,
1 of which - the ECC - is routed but left empty).

Dimiter

------------------------------------------------------
Dimiter Popoff Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------
http://www.flickr.com/photos/didi_tg...7600228621276/


On Nov 29, 11:37 am, "Nial Stewart"
<nial*[email protected] > wrote:
> > I did 6 layers as well, but my stackup is:

>
> > signal
> > GND
> > PWR
> > PWR
> > GND
> > signal
> >:-0

>
> That's not very routing efficient.
>
>
>
> > Worked the first time, actually see the prototype
> > (very first one assembled, design for an external customer)
> > board here:
> >http://tgi-sci.com/y2demo/PICT3007sc.JPG.
> > The two DDRAMs (x16 each) are close to the board centre, easy
> > to spot.
> > Here is the bare board in some better detail:
> >http://tgi-sci.com/misc/PICT0605.JPG.
> > The board is routed at 6 mil most of the time which goes
> > down to somewhat over 4 mil for the worst case angular
> > ring and for traces between BGA pads (3 traces between a
> > pair of 1.27mm spaced pads/vias.
> > Have used these rules on other boards as well, have never
> > failed me. Routing takes somewhat more head scratching (or is
> > it hear teraing... :-) ), but has always been doable.
> > Now what do I do with a 0.8mm BGA (soon to be routed here,
> > never done so far) is yet to be seen... :-)

>
> Thanks for this info.
>
> We've been working from a Micron app note which suggests 8 mil
> min clearances between data lines.
>
> On the other hand this is a short point to point connection so
> we can probably get away with a lot more than others with more
> onerous topologies.
>
> > At these low speeds, buying signal integrity tools/consultants
> > will be a sheer waste. You need neither (although ask that on
> > the SI list and you will be overwhelmed by suggestions to
> > buy all things imaginable... make sure to ignore such advice,
> > the SI tool writers and SI consultants are pretty active on that
> > list).

>
> Thanks for an alternative viewpoint.
>
> > Again, 120 MHz is nearly DC nowadays. You don't need any
> > fancy SI tools to do it.

>
> Hopefully.
>
> Nial.


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  #24 (permalink)  
Old 11-29-2007, 12:59 PM
KJ
Guest
 
Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?


"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk > wrote in
message news:[email protected]
>> Power and ground are not going to be forming a very good capacitor to
>> supply power so you're making a big compromise right there, it won't
>> be a really low inductance pathway to deliver power to the parts on
>> the board.

>
> As below, I'm not convinced this is a problem.
>
> Good _enough_ supply paths with sufficient local decoupling should do?

The problem is determining what is 'good enough'. Putting planes (or even
the voltage supply puddles and ground plane as Symon suggests) close
together gets you a very low inductance pathway for delivering the power to
the part. What your stackup had is widely separated power and ground which
is not 'good', but depending on your needs might be 'good enough'. The
other suggestion that someone posted to put the power/ground together in the
middle accomplishes the same thing and saves you two layers at the cost of
having fewer routing layers directly adjacent to the return plane. Whether
that is enough or not depends very much on your particular design.

>
>> Ideally you'd like to have two more layers, move PWR up to
>> be underneath GND and then mirror that on the bottom side (i.e. sig1,
>> GND, PWR, sig2, sig3, PWR, GND, sig4). Whether your 6 layer bites you
>> or not will depend entirely on how much switching is going on and how
>> demanding the parts are. I recently consulted on a design that had
>> the above type of stackup and the PCB was unable to deliver enough
>> 3.3V to the FPGA and would cause it to functionally upset, the board
>> failed.

>
> Might it not have been due to bad signal return path integrity or
> insufficient grounding?
>
> (I'm not arguing here, just posing the question).
>

No. In fact to try to prove to the designer that it had to do with anything
other than power (there was natural skepticism), I programmed the FPGA to
simply toggle outputs every clock cycle and the failure condition would be
when the internal phase locked loop lost lock so the only thing the PCB had
to deliver was core voltage, I/O voltage and a single input clock that went
into a PLL in the FPGA. He tried different 'filtering' on the PLL supply
voltage, we played with I/O drive strengths and limiting certain pins to
toggling at lower clock rates and it would always fail. The board only
functioned somewhat when toggling all but a handful of I/O at a lower clock
rate (1/4 of the higher speed ones). When the new board arrived, poof!
suddenly all I/O could toggle at the full clock rate, could be driven at the
full I/O current drive strength and not lose lock. The lowered inductance
(impedance) in the power delivery network that comes with the better stackup
was left as the only viable hypothesis for the failure. If you read
Ritchey's book, you'll gain a better appreciation for the PCB's role in
power delivery. The fundamental flaw that the designer I was working with
had was treating the stackup as something only to connect all the points
together and trying to minimize layers for cost reasons and being completely
lost on what you need for good power delivery. The inductance/impedance in
the path from the regulator to each load over the entire frequency range of
interest is critical.

>
> Thanks for the pointers Kevin,
>
>

You're welcome. Good luck on your design. With a bit of thought and
understanding about what is going on for delivering power and signal
terminations and image return planes (which you seem to have a basic grasp
on already) it should all work out just fine.

Kevin Jennings


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  #25 (permalink)  
Old 11-29-2007, 01:08 PM
KJ
Guest
 
Posts: n/a
Default Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?


"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk > wrote in
message news:[email protected]
>> I disagree, as does most of the research done into the subject. The use
>> of buried capacitance, typically by having adjacent power and ground
>> planes separated by as small a distance as possible (2 thou is normal),
>> has been shown to be very favorable when compared to discrete decoupling
>> caps because although the capacitance is much lower the inductance is
>> very much lower so the overall impedence is significantly lower. There is
>> an article about it here:
>> http://www.ddmconsulting.com/Design_Guides/bcguide.pdf

>
> David,
>
> I too am skeptical about the amount of decoupling that close GND/PWR plane
> coupling can provice.
>
> In that atricle above they quote 560pF/sq inch. Most BGAs are smaller
> than that.
>


It's not so much the capacitance as it is the lowered inductance that the
closely spaced planes brings you. Having a fire hydrant near a burning
house doesn't help much if you only have a garden hose to deliver the water.
The inductance of the power delivery network is the thing that delivers the
power from the source to the load.

KJ


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