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Old 11-05-2007, 06:22 AM
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Default Global Variables

i am having two PROCESS to take advantage of dual-edge behavior of the
clock pulse. one process takes care of the rising edge while the other
process takes care of the falling edge. For the two processes, they
are basically doing exactly the same thing just that one does it
during rising and the other does it during falling.. i have a problem
here, bcos i have two sets of variables that does the same thing, i
would to ask how do i change it to global variables..

example

PROCESS1
variable countera;
variable check1;

PROCESS2
variable counterb;
variable check2;

both countera/b and check1/2 are exactly the same thing but they are
being declared in the process loop. may i know how do i write the code
to change it to a shared variable that can be used in both process 1
and 2, that means i only have two variables in counter and check
rather than the four that i am having now.. pls help. thanks

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Old 11-05-2007, 12:11 PM
RCIngham
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Default Re: Global Variables

>i am having two PROCESS to take advantage of dual-edge behavior of the
>clock pulse. one process takes care of the rising edge while the other
>process takes care of the falling edge. For the two processes, they
>are basically doing exactly the same thing just that one does it
>during rising and the other does it during falling.. i have a problem
>here, bcos i have two sets of variables that does the same thing, i
>would to ask how do i change it to global variables..
>
>example
>
>PROCESS1
> variable countera;
> variable check1;
>
>PROCESS2
> variable counterb;
> variable check2;
>
>both countera/b and check1/2 are exactly the same thing but they are
>being declared in the process loop. may i know how do i write the code
>to change it to a shared variable that can be used in both process 1
>and 2, that means i only have two variables in counter and check
>rather than the four that i am having now.. pls help. thanks
>
>

Is this meant to be VHDL, and is it intended to be synthesized to an FPGA
If synthesizeable VHDL, I strongly suggest "DO NOT USE SHARED VARIABLES."

You normally declare signals in the architecture scope if you need t
write them in one process and read them in another. However, no FPGA o
which I am aware has dual edge triggered flip-flops, except in DDR I
blocks (and even there they are rather tricky).

What problem are you actually trying to solve?

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  #3 (permalink)  
Old 11-05-2007, 02:50 PM
Andy
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Default Re: Global Variables

On Nov 5, 6:11 am, "RCIngham" <[email protected]> wrote:
> >i am having two PROCESS to take advantage of dual-edge behavior of the
> >clock pulse. one process takes care of the rising edge while the other
> >process takes care of the falling edge. For the two processes, they
> >are basically doing exactly the same thing just that one does it
> >during rising and the other does it during falling.. i have a problem
> >here, bcos i have two sets of variables that does the same thing, i
> >would to ask how do i change it to global variables..

>
> >example

>
> >PROCESS1
> > variable countera;
> > variable check1;

>
> >PROCESS2
> > variable counterb;
> > variable check2;

>
> >both countera/b and check1/2 are exactly the same thing but they are
> >being declared in the process loop. may i know how do i write the code
> >to change it to a shared variable that can be used in both process 1
> >and 2, that means i only have two variables in counter and check
> >rather than the four that i am having now.. pls help. thanks

>
> Is this meant to be VHDL, and is it intended to be synthesized to an FPGA?
> If synthesizeable VHDL, I strongly suggest "DO NOT USE SHARED VARIABLES."
>
> You normally declare signals in the architecture scope if you need to
> write them in one process and read them in another. However, no FPGA of
> which I am aware has dual edge triggered flip-flops, except in DDR IO
> blocks (and even there they are rather tricky).
>
> What problem are you actually trying to solve?


DDR registers in FPGAs can be emulated with two flops and three XOR
gates (no clock gating, glitchless output, 100% STA compatible), as
has been posted on here many times. Unfortunately, there are no
synthesis tools that will implement a general two clock process with
the circuit. Those that even accept two clock processes insist on not
updating the same signal/variable on both clocks.

Andy

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