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Old 08-14-2005, 07:10 AM
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Default Glitches in Output of FSM

Hi All,
I have a state machine which produces control signals (synchronous
Reset and Enable) for a synchronous counter. The control signals are
generated based on the current state and a 8 bit data input.
I am seeing glichtes in both output control signals near the rising
clock edges. The 8 bit data input is registered.
Is there any way to get rid of the glicthes?

The VHDL code looks something like this

FSM: process(CurrentState,DataIn,Count,NewFrame,...)
begin
CntrRst <= '0'; -- counter reset
CntrEn <= '0'; -- counter enable

case CurrentState is
when State0 =>
if NewFrame = '1' then
NextState <= State1;
else
NextState <= State0;
CntrRst <= '1';
end if;

when State1 =>
case Count is
when "00000" =>
if DataIn = x"00" then
NextState <= State1;
CntrEn <= '1';
else
NextState <= State0;
CntrRst <= '1';
end if;
when "00001" =>
-- same as above except checking for a different
-- DataIn
-- All other cases test for different DataIn Values

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Old 08-14-2005, 07:23 PM
Peter Alfke
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Default Re: Glitches in Output of FSM

Sudhir,
so you have two sets of synchronous signals (hopefully synchronized by
the same global clock) and you combine them through combinatorial logic
to generate 2 control signals for the counters.
Obviously, you will generate glitches on these outputs, as a result of
prop delay differences in the combinatorial logic. But these glitches
occur a few nanoseconds AFTER the active clock edge, and they are,
therefore, irrelevant and cause no harm.
The beauty of synchronous logic is that inputs need only be stable
during the set-up time BEFORE the clock edge.
Peter Alfke, Xilinx Applications (from home)

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Old 08-14-2005, 09:47 PM
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Default Re: Glitches in Output of FSM

Peter, thanks for your reply.
Sudhir


Peter Alfke wrote:
> Sudhir,
> so you have two sets of synchronous signals (hopefully synchronized by
> the same global clock) and you combine them through combinatorial logic
> to generate 2 control signals for the counters.
> Obviously, you will generate glitches on these outputs, as a result of
> prop delay differences in the combinatorial logic. But these glitches
> occur a few nanoseconds AFTER the active clock edge, and they are,
> therefore, irrelevant and cause no harm.
> The beauty of synchronous logic is that inputs need only be stable
> during the set-up time BEFORE the clock edge.
> Peter Alfke, Xilinx Applications (from home)


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